BD8325FVT-M Datasheet, PDF (5/34 Pages) Rohm – Built-in Secondary-side Driver

BD8325FVT
⑨PWM signal generator
Through the comparator, CS1 related signal is compared with the lower voltage of SS/SD（⑦）and FB pin, and RESET
signal for Latch circuit (⑫) is produced. To be precise, the CS1 level +0.5V and the lower of SS/SD and FB level’s 1/5
are compared and the output pulse is entered into Latch circuit. In addition, when FB is lowered and SS/SD drops to
2.3V (typ), Duty0 signal turns H and RESET signal continues outputting, switching is terminated and Duty is turned to 0%.
Once the switching restarts, Duty0 will not turn H unless the voltage drops to the hysteresis voltage, 2.225V (typ).
⑩RESET condition generator
According to the outputs from each protection circuit, the block controls the signal as shown below:
(1) SS/SD 15uA charge, 15uA discharge, instantaneous discharge
(2) PWM signal（OUT, AUX, OUT2F, OUT2R）OFF
⑪SS charge/discharge controller
According to whether the protection operation is detected, the operation is shown as (1) ～ (3)
(1) 15uA Charge (SOFT_START) condition: when VCC UVLO, VREF UVLO, LINE UVLO, TSD, CS2, SAWH LVP
and external R-OPEN protections are not detected. SS/SD is clamped to VREF5V level.
(2) 15uA Discharge (SOFT_STOP) condition: when LINE, TSD and CS2 protections are detected.
Once detected, the signal is latched. The IC will not restore to SOFT START mode unless SS/SD is 0.5V.
(3) Instantaneous Discharge (discharge resistor R=0.5kΩ) condition: when VCC UVLO, VREF UVLO, SAWH LVP
and R-OPEN protection are detected.
⑫PWM signal latch block
The reference pulse signal of each output pulse is generated by SR-Flipflop.
SET: internal clock signal
RESET: PWM output signal or OCP1 signal or CLKOUT signal (Max Duty)
⑬Turn-on delay/Turn-off delay time generator
According to the dead-times, which are set by the external resistor on OUT, AUX, OUT2F and OUT2R pin in block ④,
dead-times are applied to PWM signal (⑫).
⑭PREDRIVER
The level of VREF5V is shifted to VDD level.
⑮POWMOS
This is the driver’s output stage for driving external MOSFET. It is constituted by NMOS and PMOS and the power supply
is VDD (absolute maximum rating is 20V).
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