BU90T81 Datasheet, PDF (4/14 Pages) Rohm – 27bit LVDS Transmitter

BU90T81
Datasheet
●AC characteristics
Table 3 : Switching Characteristics（VDD=1.8V, Ta=25℃ RL=100Ω CL=5ｐF RS[1:0]=HL）
Symbol
Parameter
Min
Typ
Max
Units
t_TCP
CLK OUT Period
8.93
-
50
ns
t_TCIT
CLK IN Transition time
-
-
5.0
ns
t_TCH
CLK IN High Time
0.35t_TCP
0.5t_TCP
0.65t_TCP
ns
t_TCL
CLK IN Low Time
0.35t_TCP
0.5t_TCP
0.65t_TCP
ns
t_TS
LVSMOS Data Set up to CLK IN
2.5
-
-
ns
t_TH
LVCMOS Data Hold from CLK IN
0
-
-
ns
t_LVT
T_TSUP
T_THLD
t_TOP6
t_TOP5
t_TOP4
t_TOP3
t_TOP2
t_TOP1
t_TOP0
t_TPLL
LVDS Transition Time
Differential Output
Set up Time
Differential Output
Hold time
CLKOUT=112MHz
CLKOUT=112MHz
Output Data Position 6
Output Data Position 5
Output Data Position 4
Output Data Position 3
Output Data Position 2
Output Data Position 1
Output Data Position 0
Phase Locked Loop Set Time
-
-
-
tTCP
2 ₇ - T_THLD
tTCP
3 ₇ - T_THLD
tTCP
4 ₇ - T_THLD
tTCP
5 ₇ - T_THLD
tTCP
6 ₇ - T_THLD
tTCP
7 ₇ - T_THLD
tTCP
8 ₇ - T_THLD
-
0.6
-
-
tTCP
2₇
tTCP
3₇
tTCP
4₇
tTCP
5₇
tTCP
6₇
tTCP
7₇
tTCP
8₇
-
1.5
ns
200
ｐs
200
ｐs
tTCP
2 ₇ + T_TSUP
ns
tTCP
3 ₇ + T_TSUP
ns
tTCP
4 ₇ + T_TSUP
ns
tTCP
5 ₇ + T_TSUP
ns
tTCP
6 ₇ + T_TSUP
ns
tTCP
7 ₇ + T_TSUP
ns
tTCP
8 ₇ + T_TSUP
ns
10
ｍs
●AC Timing Diagrams
LVCMOS Input
LVDS Output
Vdiff=(Tx+)-(Tx-)
Tx+
CL
RL
Tx-
LVDS Output Load
x=A,B,C.D,CLK
CLKIN ^90%
10%
tTCIT
Vdiff
80%
20%
tLVT
90%
10%
tTCIT
80%
20%
tLVT
LVCMOS Input
CLKIN VDD/2
DATA_IN V_DD/2
TCLK+
TCLK-
tTCH
tTCP
VDD/2
tTS
tTCL
tTH
VDD/2
VDD/2
tTCD
RF=L
RF=H
VOC
DATA_IN= R[7:0], G[7:0], B[7:0], VSYNC, HSYNC, DE
Figure-3 LVCMOS Input AC Timing Diagrams
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TSZ22111・15・001
4/11
TSZ02201-0L2L0V100010-1-2
23.JAN.2012 Rev.001