BR24C21 Datasheet, PDF (4/12 Pages) Rohm – ID ROM for CRT display

Memory ICs
BR24C21 / BR24C21F / BR24C21FJ / BR24C21FV
!Timing charts
SYNCHRONOUS DATA TIMING
SCL
SDA
(IN)
SDA
(OUT)
tHD : STA
tBUF
tR
tF
tHIGH
tSU : DAT
tLOW
tPD
tHD : DAT
SCL
SDA
tSU : STA
tHD : STA
tSU : STO
START BIT
Fig.7
•SDA data is latched into the chip at the rising edge of the SCL clock.
•Output data toggles at the falling edge of the SCL clock.
WRITE CYCLE TIMING
SCL
STOP BIT
SDA
D0
WRITE DATA
(n)
WRITE ENABLE TIMING
SCL
ACK
tWR
STOP CONDITION
START CONDITION
Fig.8
START BIT
STOP BIT
SDA
VCLK
tVSU
WRITE COMMAND
Fig.9
tVHD