BD9855MWV Datasheet, PDF (4/5 Pages) Rohm – Silicon Monolithic Integrated Circuit

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○Operation Notes
1.) Absolute maximum ratings
Use of the IC in excess of absolute maximum ratings such as the applied voltage or operating temperature range may result in IC deterioration or damage.
Assumptions should not be made regarding the state of the IC (short mode or open mode) when such damage is suffered. A physical safety measure such
as a fuse should be implemented when use of the IC in a special mode where the absolute maximum ratings may be exceeded is anticipated.
2.) GND potential
Ensure a minimum GND pin potential in all operating conditions. In addition, ensure that no pins other than the GND pin carry a voltage lower than or equal
to the GND pin(except INV4 terminal), including during actual transient phenomena.
3.) Thermal design
Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions.
4.) Inter-pin shorts and mounting errors
Use caution when orienting and positioning the IC for mounting on printed circuit boards. Improper mounting may result in damage to the IC. Shorts between
output pins or between output pins and the power supply and GND pin caused by the presence of a foreign object may result in damage to the IC.
5.) Operation in a strong electromagnetic field
Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to malfunction.
6.) Common impedance
Power supply and ground wiring should reflect consideration of the need to lower common impedance and minimize ripple as much as possible (by making
wiring as short and thick as possible or rejecting ripple by incorporating inductance and capacitance).
7.) Voltage of CTL pin
The threshold voltages of CTL pin are 0.8V and 2.0V. STB state is set below 0.8V while action state is set beyond 2.0V.
The region between 0.8V and 2.0V is not recommended and may cause improper operation.
The rise and fall time must be under 10msec. In case to put capacitor to STB pin, it is recommended to use under 0.01μF.
8.) Thermal shutdown circuit (TSD circuit)
This IC incorporates a built-in thermal shutdown circuit (TSD circuit). The TSD circuit is designed only to shut the IC off to prevent runaway thermal operation.
Do not continue to use the IC after operating this circuit or use the IC in an environment where the operation of the thermal shutdown circuit is assumed.
9.) IC pin input
This monolithic IC contains P+ isolation and PCB layers between adjacent elements in order to keep them isolated.
P/N junctions are formed at the intersection of these P layers with the N layers of other elements to create a variety of parasitic elements.
For example, when a resistor and transistor are connected to pins as shown in following chart,
 the P/N junction functions as a parasitic diode when GND > (Pin A) for the resistor or GND > (Pin B) for the transistor (NPN).
 Similarly, when GND > (Pin B) for the transistor (NPN), the parasitic diode described above combines with the N layer of other adjacent
elements to operate as a parasitic NPN transistor.
The formation of parasitic elements as a result of the relationships of the potentials of different pins is an inevitable result of the IC's architecture. The
operation of parasitic elements can cause interference with circuit operation as well as IC malfunction and damage. For these reasons, it is necessary to use
caution so that the IC is not used in a way that will trigger the operation of parasitic elements, such as by the application of voltages lower than the GND
(PCB) voltage to input and output pins.
（Pin A）
Resistance
（Pin B） C
Transistor (NPN)
B
E
P^＋
N
P
N
P^＋
N
P substrate
Parasitic elementals
P^＋
N
N
P
N
GND
P^＋
N
P substrate
GND
Parasitic elementals
（PinＡ）
Parasitic diode
GND
Fig.4 Simplified structure of a Bipolar IC
REV. C