BD9839MWV Datasheet, PDF (4/5 Pages) Rohm – Silicon Monolithic Integrated Circuit

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● Operation Notes
１.) Absolute maximum ratings
Use of the IC in excess of absolute maximum ratings such as the applied voltage or operating temperature range may result in IC deterioration or damage. Assumptions should not
be made regarding the state of the IC (short mode or open mode) when such damage is suffered. A physical safety measure such as a fuse should be implemented when use of the
IC in a special mode where the absolute maximum ratings may be exceeded is anticipated.
２.) GND potential
Ensure a minimum GND pin potential in all operating conditions. In addition, ensure that no pins other than the GND pin carry a voltage lower than or equal to the GND pin, including
during actual transient phenomena.
３.) Thermal design
Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions.
４.) Inter-pin shorts and mounting errors
Use caution when orienting and positioning the IC for mounting on printed circuit boards. Improper mounting may result in damage to the IC. Shorts between output pins or between
output pins and the power supply and GND pin caused by the presence of a foreign object may result in damage to the IC.
５.) Operation in a strong electromagnetic field
Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to malfunction.
６.) Common impedance
Power supply and ground wiring should reflect consideration of the need to lower common impedance and minimize ripple as much as possible (by making wiring as short
and thick as possible or rejecting ripple by incorporating inductance and capacitance).
７.) Voltage of CTL pin
The threshold voltages of CTL pin are 0.8V and 2.0V. STB state is set below 0.8V while action state is set beyond 2.0V.
The region between 0.8V and 2.0V is not recommended and may cause improper operation.
The rise and fall time must be under 10msec. In case to put capacitor to STB pin, it is recommended to use under 0.01μF.
８.) Thermal shutdown circuit (TSD circuit)
This IC incorporates a built-in thermal shutdown circuit (TSD circuit). The TSD circuit is designed only to shut the IC off to prevent runaway thermal operation. Do not continue to use the
IC after operating this circuit or use the IC in an environment where the operation of the thermal shutdown circuit is assumed.
９.) Applications with modes that reverse VCC and pin potentials may cause damage to internal IC circuits.
For example, such damage might occur when VCC is shorted with the GND pin while an external capacitor is charged. It is recommended to insert a diode for preventing back
current flow in series with VCC or bypass diodes between VCC and each pin.
10.) Relationship between PVCC - VCC
Because diode was connecting between PVCC (Anode) – VCC (Cathode) for prevent electrostatic breakdown,
it must be set PVCC – VCC < 0.3V voltage relationship.
11.) Rush current at the time of power supply injection.
An IC which has plural power supplies, or CMOS IC could have momentaly rush current at the time of power supply injection.
Because there exists inside logic uncertainty state. Please take care about power supply coupling capacity and width of power
Supply and GND pattern wiring.
12.) Please use it so that VCC and PVCC terminal should not exceed the absolute maximum ratings. Ringing might be caused by L element of the pattern
according to the position of the input capacitor, and ratings be exceeded. Please will assume the example of the reference ,the distance of IC and capacitor, use it by 5.0mm or less when
thickness of print pattern are 35um, pattern width are 1.0mm.
13.) Testing on application boards
When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress. Always discharge capacitors after each process or step.
Ground the IC during assembly steps as an antistatic measure, and use similar caution when transporting or storing the IC. Always turn the IC's power supply off before connecting it to
or removing it from a jig or fixture during the inspection process.
14.) IC pin input
This monolithic IC contains P+ isolation and PCB layers between adjacent elements in order to keep them isolated.
P/N junctions are formed at the intersection of these P layers with the N layers of other elements to create a variety of parasitic elements.
For example, when a resistor and transistor are connected to pins as shown in following chart,
 the P/N junction functions as a parasitic diode when GND > (Pin A) for the resistor or GND > (Pin B) for the transistor (NPN).
 Similarly, when GND > (Pin B) for the transistor (NPN), the parasitic diode described above combines with the N layer of other adjacent elements to operate as a
parasitic NPN transistor.
The formation of parasitic elements as a result of the relationships of the potentials of different pins is an inevitable result of the IC's architecture. The operation of parasitic elements
can cause interference with circuit operation as well as IC malfunction and damage. For these reasons, it is necessary to use caution so that the IC is not used in a way that will
trigger the operation of parasitic elements, such as by the application of voltages lower than the GND (PCB) voltage to input and output pins.
(PinA)
Resistance
Ｐ^＋
ï¼®
ï¼°
Ｐ^＋
ï¼®
ï¼®
P substrate
ＧＮＤ
Parasitic diode
Transistor (NPN)
(PinB)
ï¼¢
ï¼£
ï¼¥
(PinA)
Parasitic diode
ï¼®
ＧＮＤ
Ｐ^＋
ï¼°
Ｐ^＋
ＧＮＤ
(PinB)
ï¼®
ï¼®
ï¼®
P substrate
ＢＣ
ＧＮＤ
ï¼¥
Parasitic elementals
Other adiacent components
ＧＮＤ
Parasitic diode
REV. C