BD9275F Datasheet, PDF (4/5 Pages) Rohm – Silicon Monolithic Integrated Circuit

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〇NOTE FOR USE
1. This product is produced with strict quality control, but might be destroyed if used beyond its absolute maximum ratings.
Once IC is destroyed, failure mode will be difficult to determine, like short mode or open mode. Therefore, physical
protection countermeasure, like fuse is recommended in case operating conditions go beyond the expected absolute maximum
ratings.
2. The circuit functionality is guaranteed within of ambient temperature operation range as long as it is within recommended
operating range. The standard electrical characteristic values cannot be guaranteed at other voltages in the operating
ranges, however the variation will be small.
3. Mounting failures, such as misdirection or miscounts, may harm the device.
4. A strong electromagnetic field may cause the IC to malfunction.
5. The GND pin should be the location within ±0.3V compared with the PGND pin. ALL voltage should be under VCC voltage
+0.3V
6. BD9275F incorporate a built-in thermal shutdown circuit (TSD circuit). The thermal shutdown circuit (TSD circuit) is
designed only to shut the IC off to prevent runaway thermal operation. It is not designed to protect the IC or guarantee
its operation of the thermal shutdown circuit is assumed.
7. When modifying the external circuit components, make sure to leave an adequate margin for external components actual
value and tolerance as well as dispersion of the IC.
8. About the external FET, the parasitic Capacitor may cause the gate voltage to change, when the drain voltage is switching.
Make sure to leave adequate margin for this IC variation.
9. Under operating CP charge (under error mode) analog dimming and burst dimming are not operate.
10. Under operating Slow Start Control (SS is less than 2.5V), It does not operate Timer Latch.
11. By STB voltage is changed to 2 states. Therefore, do not input STB pin voltage between one state and the other state
(0.8～2.0V).
12. The pin connected a connector need to connect to the resistor for electrical surge destruction.
13. This IC is a monolithic IC which (as shown is Fig-1) has P⁺ substrate and between the various pins. A P-N junction is
formed from this P layer of each pin. For example, the relation between each potential is as follows,
○(When GND > PinB and GND > PinA, the P-N junction operates as a parasitic diode.)
○(When PinB > GND > PinA, the P-N junction operates as a parasitic transistor.)
Parasitic diodes can occur inevitably in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits as well as operation faults and physical damage. Accordingly you must not use methods by
which parasitic diodes operate, such as applying a voltage that is lower than the GND (P substrate) voltage to an input
pin.
Resistance
Transistor (NPN)
(PinA)
(PinB)
B
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E
GND
P^＋
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P
P^＋
N
P substrate
GND
Parasitic diode
N
N
N
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P substrate
GND
Parasitic diode
(PinA)
Parasitic diode
GND
(PinB)
B
C
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GND
Parasitic diode
Other adjacent components
Fig-1 Simplified structure of a Bipolar IC
REV. B