BD9217F Datasheet, PDF (4/5 Pages) Rohm – Silicon Monolithic Integrated Circuit

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〇NOTE FOR USE
１. When designing the external circuit, including adequate margins for variation between external devices and IC. Use adequate margins for steady
state and transient characteristics.
２. The circuit functionality is guaranteed within of ambient temperature operation range as long as it is within recommended operating range. The
standard electrical characteristic values cannot be guaranteed at other voltages in the operating ranges, however the variation will be small.
３. Mounting failures, such as misdirection or miscounts, may harm the device.
４. A strong electromagnetic field may cause the IC to malfunction.
５. The GND pin should be the location within ±0.3V compared with the PGND pin.
６. If the voltage between VCC and I/O pins or GND and I/O pins is in opposite from the normal potential difference, unusual current flow into pins
may occur which can destroy the IC. To avoid such occurrence it is recommended to place protection diodes for prevention against backward
current flow.
７. BD9217F/BD9217FV incorporate a built-in thermal shutdown circuit (TSD circuit). The thermal shutdown circuit (TSD circuit) is designed only
to shut the IC off to prevent runaway thermal operation. It is not designed to protect the IC or guarantee its operation of the thermal shutdown
circuit is assumed.
８. Absolute maximum ratings are those values that, if exceeded, may cause the life of a device to become significantly shortened. Moreover, the
exact failure mode caused by short or open is not defined. Physical countermeasures, such as a fuse, need to be considered when using a
device beyond its maximum ratings.
９. About the external FET, the parasitic Capacitor may cause the gate voltage to change, when the drain voltage is switching. Make sure to leave
adequate margin for this IC variation.
１０. By STB voltage, BD9217FV are changed to 2 states. Therefore, do not input STB pin voltage between one state and the other state (0.8～
2.0V).
１１. The pin connected a connector need to connect to the resistor for electrical surge destruction.
１２．This IC is a monolithic IC which (as shown is Fig.1)has P⁺ substrate and between the various pins. A P-N junction is formed from this P layer
of each pin. For example, the relation between each potential is as follows,
○(When GND > PinB and GND > PinA, the P-N junction operates as a parasitic diode.)
○(When PinB > GND > PinA, the P-N junction operates as a parasitic transistor.)
Parasitic diodes can occur inevitably in the structure of the IC. The operation of parasitic diodes can result in mutual interference among
circuits as well as operation faults and physical damage. Accordingly you must not use methods by which parasitic diodes operate, such as
applying a voltage that is lower than the GND (P substrate) voltage to an input pin.
Resistance
(PinA)
P^＋
ï¼®
P
P^＋
N
P substrate
GND
Parasitic diode
Transistor (NPN)
(PinB)
B
C_ï¼£
E
N
GND
N
N
ï¼®
P substrate
GND
Parasitic diode
(PinB)
(PinA)
Parasitic diode
B _ï¼¢^{C ï¼£}
E_ï¼¥
GND
GND
Other adjacent c_Pom_arp_aso_in_ticen_dt_is_ode
Fig.1 Simplified structure of a Bipolar IC
REV. C