BD9203EFV Datasheet, PDF (4/5 Pages) Rohm – Silicon Monolithic Integrated Circuit

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○ Operation Notes
1) Absolute maximum ratings
An excess in the absolute maximum rating, such as supply voltage, temperature range of operating conditions, etc., can break down
the devices, thus making impossible to identify breaking mode, such as a short circuit or an open circuit. If any over rated values will
expect to exceed the absolute maximum ratings, consider adding circuit protection devices, such as fuses.
2) GND voltage
The potential of GND pin must be minimum potential in all condition. As an exception, the circuit design allows voltages up to -0.3 V
to be applied to the ICT pin.
3) Thermal design
Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions.
4) Inter-pin shorts and mounting errors
Use caution when positioning the IC for mounting on printed circuit boards. The IC may be damaged if there is any connection error or
if pins are shorted together.
5) Actions in strong electromagnetic field
Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to malfunction.
6) Mutual impedance
Power supply and ground wiring should reflect consideration of the need to lower mutual impedance and minimize ripple
as much as possible (by making wiring as short and thick as possible or rejecting ripple by incorporating inductance and capacitance).
7) Regarding input pin of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated. P-N junctions
are formed at the intersection of these P layers with the N layers of other elements, creating a parasitic diode or transistor. For example,
as shown in the figures below, the relation between each potential is as follows:
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes can occur inevitable in the structure of the IC. The operation of parasitic diodes can result in mutual interference
among circuits, operational faults, or physical damage. Accordingly, methods by which parasitic diodes operate, such as applying
a voltage that is lower than the GND (P substrate) voltage to an input pin, should not be used. Although the circuit design allows voltages
up to -0.3 V to be applied to the ICT pin, voltages lower than this may cause the behavior described above. Use caution when designing
the circuit.
(Pin A)
P⁺
N
Resistor
P
N
P substrate
P⁺
N
(Pin B)
B
TCransistor (NPN)
E
P⁺
N
N
P
N
GND
P⁺
N
P substrate
Parasitic elements
GND
Parasitic elements
GND
(Pin A)
(Pin B)
B
Parasitic elements
GND
Other Adjacent Elements
Simplified structure of a Monolithic IC
C
E
GND
Parasitic elements
REV. Ａ