BD9470AEFV Datasheet, PDF (33/39 Pages) Rohm – White LED driver for medium sized and large sized LCD back light

BD9470AFM・BD9470AEFV
4. Caution on use
1.) We pay utmost attention to the quality control of this product. However, if it exceeds the absolute maximum ratin
gs including applied voltage and operating temperature range, it may lead to its deterioration or breakdown. Furth
er, this makes it impossible to assume a breakdown state such as short or open circuit mode. If any special mod
e to exceed the absolute maximum ratings is assumed, consider adding physical safety measures such as fuses.
2.) Making a reverse connection of the power supply connector can cause the IC to break down. To protect the IC f
orm breakdown due to reverse connection, take preventive measures such as inserting a diode between the exter
nal power supply and the power supply pin of the IC.
3.) Since current regenerated by back electromotive force flows back, take preventive measures such as inserting a c
apacitor between the power supply and the ground as a path of the regenerative current and fully ensure that ca
pacitance presents no problems with characteristics such as lack of capacitance of electrolytic capacitors causes a
t low temperatures, and then determine the power supply line. Provide thermal design having an adequate margin
in consideration of power dissipation (Pd) in the practical operating conditions.
4.) The potential of the GND pin should be maintained at the minimum level in any operating state.
5.) Provide thermal design having an adequate margin in consideration of power dissipation (Pd) in the practical oper
ating conditions.
To mount the IC on a printed circuit board, pay utmost attention to the direction and displacement of the IC. Furthermore,
the IC may get damaged if it is mounted in an erroneous manner or if a short circuit is established due to foreign matters
entered between output pins or between output pin and power supply GND pin.
6.) Note that using this IC in strong magnetic field may cause it to malfunction.
7.) Please set the output Tr not to over absolute Maximum Ratings and ASO. CMOS IC and plural power supply IC
have a possible to flow lush current momentarily. Please note VCC capacitor, VCC and GND layout.
8.) This IC has a built-in thermal-protection circuit (TSD circuit).
The thermal-protection circuit (TSD circuit) is a circuit absolutely intended to protect the IC from thermal runaway,
not intended to protect or guarantee the IC. Consequently, do not use the IC based on the activation of this TS
D circuit for subsequent continuous use and operation of the IC.
9.) When testing the IC on a set board with a capacitor connected to the pin, the IC can be subjected to stress. In
this case, be sure to discharge the capacitor for each process. In addition, to connect the IC to a jig up to the t
esting process, be sure to turn OFF the power supply prior to connection, and disconnect the jig only after turnin
g OFF the power supply.
10.) This monolithic IC contains P + Isolation and P substrate layers between adjacent elements in order to keep them
isolated.
P-N junctions are formed at the intersections of these P layers and the N layers of other elements, thus making up
different types of parasitic elements.
For example, if a resistor and a transistor is connected with pins respectively as shown in Fig.
When GND>(Pin A) for the resistor, or when GND>(Pin B) for the transistor (NPN), P-N junctions operate as a a
parasitic diode.
When GND>(Pin B) for the transistor (NPN), the parasitic NPN transistor operates by the N layer of other element
adjacent to the parasitic diode aforementioned.
Due to the structure of the IC, parasitic elements are inevitably formed depending on the relationships of potential. The
operation of parasitic diodes can result in interferences in circuit operation, leading to malfunctions and eventually
breakdown of the IC. Consequently, pay utmost attention not to use the IC for any applications by which the parasitic
elements are operated, such as applying a voltage lower than that of GND (P substrate) to the input pin.
(Pin A)
Resistor
(Pin B)
Transistor (NPN)
B
C
E
P
N
P
N
P
N
P substrate
GND
Parasitic element
P
N
N
P
N
P substrate
GND
P
N
GND
Parasitic element
(Pin B)
(Pin A)
BC
E
Parasitic element
ＧＮＤ
GND
Adjacent other elements
Parasitic
Figure 35. Example of Simple Structure of
Status of this document
Monolithic IC
The Japanese version of this document is formal specification. A customer may use this translation version only for a
reference to help reading the formal version.
If there are any differences in translation version of this document formal version takes priority
www.rohm.com
© 2013 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
33/35
TSZ02201-0F10C1002000-1-2
19.Oct.2013 Rev.003