BU99901GUZ-W_10 Datasheet, PDF (3/17 Pages) Rohm – WL-CSP EEPROM family I2C BUS

BU99901GUZ-W
●Sync data input/output timing
tR
tF
tHIGH
SCL
(Input)
SDA
tHD :STA
tSU :DAT tLOW
tHD :DAT
SDA
(Output)
tBUF
tPD
tDH
○Input read at the rise edge of SCL
○Data output in sync with the fall of SCL
Fig.1-(a) Sync data input / output timing
SCL
tSU:STA
SDA
tHD:STA
tSU:STO
START BIT
Fig.1-(b) Start - stop bit
STOP BIT
SCL
SDA
D0
WRITE DATA(n)
ACK
STOP
CONDITION
tWR
START
CONDITION
Fig.1-(c) Write cycle timing
Technical Note
SCL
SDA
DATA(1)
D1 D0 ACK
WP
DATA(n)
ACK
t WR
Stop condition
tSU：WP
ｔHD：WP
Fig.1-(d) WP timing at write execution
SCL
SDA
WP
DATA(1)
D1 D0 ACK
DATA(n)
tHIGH:WP
ACK
tW_tWR_R
○At write execution, in the area from the D0 taken clock rise of the first
DATA(1), to tWR, set WP= 'LOW'.
○By setting WP "HIGH" in the area, write can be cancelled.
When it is set WP = 'HIGH' during tWR, write is forcibly ended, and data of
address under access is not guaranteed, therefore write it once again.
Fig.1-(e) WP timing at write cancels
●Block diagram
32Kbit EEPROM array
12 bit
A dddre ss
decoder
12bit
Slave - word
address register
8bit
Da ta
register
TEST
GND
START
Control circuit
STOP
ACK
High voltage
generating circuit
Power source
voltage detection
TEST terminal,please connect GND
Fig.2 Block diagram
Vcc
WP
SCL
SDA
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3/16
2010.09 - Rev.A