BR24T-E Datasheet, PDF (3/22 Pages) Rohm – Other devices than EEPROM can be connected to the same port, saving microcontroller port

BR24T□□□□Series
Technical Note
●Action timing characteristics (Unless otherwise specified, Ta=－40～+85℃, VCC=1.7～5.5V)
Parameter
Limits
Symbol
Unit
Min.
Typ.
Max.
SCL frequency
fSCL
－
－
400
kHz
Data clock “HIGH“ time
tHIGH
0.6
－
－
µs
Data clock “LOW“ time
SDA, SCL rise time ^*1
SDA, SCL fall time ^*1
tLOW
1.2
－
－
µs
tR
－
－
1.0
µs
tF
－
－
1.0
µs
Start condition hold time
tHD:STA
0.6
－
－
µs
Start condition setup time
tSU:STA
0.6
－
－
µs
Input data hold time
tHD:DAT
0
－
－
ns
Input data setup time
tSU:DAT
100
－
－
ns
Output data delay time
tPD
0.1
－
0.9
µs
Output data hold time
tDH
0.1
－
－
µs
Stop condition setup time
tSU:STO
0.6
－
－
µs
Bus release time before transfer start
tBUF
1.2
－
－
µs
Internal write cycle time
tWR
－
－
5
ms
Noise removal valid period (SDA, SCL terminal)
tI
－
－
0.1
µs
WP hold time
tHD:WP
1.0
－
－
µs
WP setup time
tSU:WP
0.1
－
－
µs
WP valid time
tHIGH:WP 1.0
－
－
µs
*1 Not 100% TESTED.
Condition Input data level:VIL=0.2×Vcc VIH=0.8×Vcc
Input data timing refarence level: 0.3×Vcc/0.7×Vcc
Output data timing refarence level: 0.3×Vcc/0.7×Vcc
Rise/Fall time : ≦20ns
●Sync data input / output timing
tR
tF
tHIGH
SCL
70%
70%
SDA
(input)
tBUF
30%
70% 70%
30%
tSU:DAT
tLOW
70%
70%
30%
tPD
70%
30%
tHD:DAT
70%
30%
tDH
SDA
(output)
70%
30%
70%
30%
○Input read at the rise edge of SCL
○Data output in sync with the fall of SCL
Fig.1-(a) Sync data input / output timing
70%
DATA(1)
D1
D0 ACK
DATA(n)
ACK
70%
tWR
30%
30%
tSU:WP
tHD:WP
STOP CONDITION
Fig.1-(d) WP timing at write execution
70%
70%
tSU:STA
tHD:STA
70%
30%
START CONDITION
70%
tSU:STO
30%
STOP CONDITION
Fig.1-(b) Start-stop bit timing
DATA(1)
D1 D0 ACK
DATA(n)
tHIGH:WP
70%
70%
ACK
70%
tWR
Fig.1-(e) WP timing at write cancel
D0
write data
(n-th address)
ACK
70%
70%
tWR
STOP CONDITION START CONDITION
Fig.1-(c) Write cycle timing
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2011.03 - Rev.A