BD9759MWV Datasheet, PDF (3/5 Pages) Rohm – Silicon Monolithic Integrated Circuit

○ Block Diagram
3/4
○ Package
BD9759MW
LOT No.
Fig.1
○ Pin Description
Pin Name
VCC
PVCC
PVCCH
PVCCL
PGND1,23,4,56
,7
GND
VREGA
OUT1H,OUT5
REGIN
REGOUT
REGADJ
LEDIN
LEDOUT
LEDREF
Hx2,3,4
VREF5
Description
Power supply
Power supply for the output circuit
Power supply for the output circuit
(High side)
Power supply for the output circuit
(Low side)
Ground terminal for internal FET
Ground terminal
VREGA output
Terminal for connecting gate of
OUT1H, OUT5 PMOS
Input terminal for REG
Output terminal for REG
Feed back terminal for REG
Input terminal for LED
Output terminal for LED
Feed back terminal for LED
Input terminal for synchronous High
side switch
Base bias voltage
Pin Name
VOUT1
Lx2,3,4,6,7
INV 1～4,6,7
INV7I
NON5
Lx11
Lx12
RT
SCP
STBREG
STBLED
STB123,
4,5,6,7
SWIN6,7
SWOUT6,7
CMINUS
-
Description
CH1 output voltage
Terminal for connecting inductors
Error AMP inverted input
Error AMP inverted input
Error AMP non inverted input
Terminal for connecting inductor for CH1 input
Terminal for connecting inductor for CH1 output
For connecting a register to set the OSC freqency
For connecting a capacitor to set up the delay time
of the SCP
REG ON/OFF switch Active ‘H’
LED ON/OFF switch Active ‘H’
CH1～CH7 ON/OFF switch Active ‘H’
Input terminal for Lord SW
Output Terminal for Load SW
Terminal for connecting capacitor for Charge Pump
-
Fig.2
○ Pin Assignment
42 41 40 39 38 37 36 35 34 33 32 31 30 29
43 STB7
44 STB6
45 STB5
46 OUT5
47 PGND56
48 LX6
49 SWIN6
50 SWOUT6
51 SWOUT7
52 SWIN7
53 LX7
54 PGND7
55 LEDREF
56 LEDOUT
BD9759MWV
PVCC 28
OUT1H 27
LX11 26
LX11 25
PGND1 24
PGND1 23
LX12 22
LX12 21
VOUT1 20
HX4 19
LX4 18
PGND4 17
CMINUS 16
PVCCH 15
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Fig.3
REV. A