BU94501AMUV Datasheet, PDF (27/73 Pages) Rohm – AAC/WMA/MP3 +SD Memory Card + iPod

BU9450xAxxx series
Datasheet
9.4 Protocol to read to the master
When sending the received data from the slave to the master using the I²C bus, be sure to conform to the transfer
protocol shown in Figure 28. First, transfer the status read command (step1). Then, input SCL clock of required
bytes in step2 to read the status.
If the device status is BUSY when receiving the device status or the data within the memory, the I²C bus may be
occupied by the device in BUSY. This LSI transfers the data to the master to avoid such occupation of the bus.
However, as the BUSY status still exists internally, the proper data may not be transferred in BUSY. To cope with
this situation, the first byte of the transfer data (step2) is used to judge whether the transferred data is valid or
invalid. After addressing from the master to the slave, if the 0 bit of the first byte of the transfer data immediately
after requiring the data transfer is 0, the data transferred from the slave is valid. If the 0 bit of the first byte is 1, it
shows the BUSY status. Thus, judge all the transferred data to be invalid. If this happens, retry Step1 to send
commands to read the status.
The first byte of the transferred data (step2) can be readable as the BUSY byte. Please read the status after
sending the status read command (step1). In addition, internal statuses other than BUSY shown in Table 6. can
be read.
The first byte of the transferred data (step2) can be readable as the BUSY byte. Please read the status after
sending the status read command (step1). In addition, internal statuses other than BUSY shown in Table.7 can
be read.
Figure 29. shows the relationship between the transferred data and BUSY.
Table 6. BUSY Byte Structure
bit
STATUS
7
0
6
0
5
0
4
PRECOM
3
IRPTO
2
SEARCH
1
MCHNG
0
BUSY
Step1
S Slave Address R/W A Data(8bit) A
Data(8bit)
Step2
"0"(write)
S Slave Address R/W A BUSY(8bit) A Data(8bit) A
"1"(read)
From Master to Slave
A = Acknowledge(SDA low)
From Slave to Master
A = No Acknowledge(SDA high)
S = Start Condition
P = Stop condition
A/A P
Data(8bit)
Figure 28. Status Reception Protocol
AP
I2C Step1 command
BUSY
S Slave Address R A BUSY[0]=1 A Data(8bit) A
BUSY byte
Data(8bit)
AP
Step1 command
S Slave Address R A
0x00
A Data(8bit) A
BUSY byte for Status
Figure 29. Relationship between Transferred Data and BUSY
Data(8bit)
AP
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