BR24L01A-W Datasheet, PDF (23/41 Pages) Rohm – I2C BUS 1Kbit (128 x 8bit) EEPROM

BR24L□□-W Series,BR24S□□□-W Series
●Sync data input/output timing
tR
tF tHIGH
SCL
SDA
(I(n入pu力t))
SDA
(O⁽u^出tp^力u⁾t)
tHD:STA
tBUF
tSU:DAT tLOW
tHD:DAT
tPD
tDH
○Input read at the rise edge of SCL
○Data output in sync with the fall of SCL
Fig.1-(a) Sync data input / output timing
Technical Note
SCL
tSU:STA
SDA
tHD:STA
tSU:STO
START BIT
STOP BIT
Fig.1-(b) Start - stop bit timing
SCL
SDA
D0
WRITE DATA(n)
ACK
STOP
CONDITION
tW R
START
CONDITION
Fig.1-(c) Write cycle timing
SCL
SDA
DATA(1)
D1 D0 ACK
WP
DATA(n)
ACK
ｔWR
Sスtoトpッcプoコnンdiデtioィnション
tSU：WP
ｔHD：WP
Fig.1-(d) WP timing at write execution
SCL
SDA
DATA(1)
D1 D0 ACK
DATA(n)
tHIGH:WP
WP
ACK
tWtWRR
○At write execution, in the area from the D0 taken clock rise of the first
DATA(1), to tWR, set WP= 'LOW'.
○By setting WP "HIGH" in the area, write can be cancelled.
When it is set WP = 'HIGH' during tWR, write is forcibly ended, and data
of address under access is not guaranteed, therefore write it once again.
Fig.1-(e) WP timing at write cancel
●Block diagram
*2
A0 1
*2
A1 2
*1
10bit
11bi t
12bit
13bit
14bit
15bit
A dddre ss
decoder
8Kbit～256Kbit EEPROM array
*1 10bit
11bit
12bit
13bit
14bit
15bit
Slave - word
address register
8bit
Da ta
register
*2 _{A2 3}
START
Control circuit
STOP
ACK
GND 4
High voltage
generating circuit
Power source
voltage detection
＊_{1 10bit: BR24S08-W}
11bit: BR24S16-W
12bit: BR24S32-W
13bit: BR24S64-W
14bit: BR24S128-W
15bit: BR24S256-W
＊_{2 A0, A1= Don’t use: BR24S08-W}
A0, A1, A2= Don’t use: BR24S16-W
Fig.2 Block diagram
8 Vcc
7 WP
6 SCL
5 SDA
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2009.09 - Rev.D