BU9897GUL-W Datasheet, PDF (2/5 Pages) Rohm – Silicon Monolithic Integrated Circuit

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◇MEMORY CELL CHARACTERISTICS (Ta=25℃, Vcc=1.7～5.5V)
Parameter
Specification
Min.
Typ.
Max.
Write/Erase Cycle
*1
1,000,000
-
-
Data Retention
*1
40
-
-
○Initial Data FFh in all address.
Unit
Cycles
Years
*1 Not 100% TESTED
◇DC OPERATING CHARACTERISTICS
Parameter
"H" Input Voltage1
Symbol
VIH1
Specification
Unit
Min. Min. Min.
0.7Vcc － Vcc+1.0 V
Specification
"L" Input Voltage1
"L" Output Voltage1
"L" Output Voltage2
Input Leakage
Current
Output Leakage
Current
Operating Current
VIH2
VOL1
VOL2
ILI
ILO
ICC1
ICC2
Standby Current
ISB
-0.3 － 0.3Vcc V
－
－
0.4
－
－
0.2
V
IOL=3.0mA，2.5V≦Vcc≦
5.5V（SDA）
V
IOL=0.7mA，1.7V≦Vcc＜
2.5V（SDA）
-1
－
1
μA
VIN=0V～Vcc
-1
－
1
μA VOUT=0V～Vcc（SDA）
Vcc=5.5V,fSCL=400ｋHz，
－
－
2.5 mA
tWR=5ms
Byte Write,Page Write
Vcc=5.5V,fSCL=400ｋHz
－
－
0.5
ｍA Random Read,Current
Read,Sequential Read
－
－
2.0
μA
Vcc=5.5V,SDA,SCL=Vcc
A0,A1,A2=GND,WP=GND
◇ AC OPERATING CHARACTERISTICS
(Unless otherwise specified Ta=-40～85℃, Vcc=1.7～5.5V)
Parameter
Symbol
Specification
Min.
Typ.
Max.
Unit
Clock Frequency
fSCL
－
Data Clock High
Period
tHIGH
0.6
Data Clock Low
Period
tLOW
1.2
SDA and SCL
Rise Time *1
tR
－
SDA and SCL
Fall Time *1
tF
－
Start Condition
Hold Time
tHD:STA
0.6
Start Condition
Setup Time
tSU:STA
0.6
Input Data Hold
Time
tHD:DAT
0
Input Data Setup
Time
tSU:DAT
100
Output Data
Delay Time
tPD
0.1
Output Data Hold
Time
tDH
0.1
Stop Condition
Setup Time
tSU:STO
0.6
Bus Free Time
tBUF
1.2
－
400
kHz
－
－
μs
－
－
Μs
－
0.3
Μs
－
0.3
Μs
－
－
Μs
－
－
μs
－
－
ns
－
－
ns
－
0.9
μs
－
－
μs
－
－
μs
－
－
μs
Write Cycle Time
tWR
－
－
5
ns
Noise Spike
Width (SDA and
tI
SCL)
－
－
0.1
μs
WP Hold Time
tHD:WP
0
－
－
ns
WP Setup Time
tSU:WP
0.1
－
－
μs
WP High Period
tHIGH:WP
1.0
－
－
μs
*1 Not 100% TESTED
◇BLOCK DIAGRAM
A0 B3
A1 C3
A2 C2
128Kbit EEPROM ARRAY
14bit
ADDRESS
SLAVE, WORD
DECODER 14bit ADDRESS REGISTER
8bit
DATA
REGISTER
START
STOP
CONTROL LOGIC
ACK
◇PIN No. NAME
A3 Vcc
A2 WP
A1 SCL
PIN No.
A1
A2
A3
A4
B1
B3
B4
C1
C2
C3
C4
PIN NAME
SCL
WP
Vcc
GND
SDA
A0
GND
GND
A2
A1
GND
GND C1 HIGH VOLTAGE GEN.
VCC LEVEL DETECT
B1 SDA
Fig.-1 BLOCK DIAGRAM
REV. B