BU9880GUL-W Datasheet, PDF (2/5 Pages) Rohm – Silicon Monolithic Integrated Circuit

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◇ MEMORY CELL CHARACTERISTICS (Ta=25℃, Vcc=1.7～5.5V)
Parameter
Specification
Unit
Min.
Typ.
Max.
Write/Erase Cycle
*1
1,000,000
-
-
Cycles
Data Retention
*1
40
-
-
Years
○Initial Data FFh in all address.
*1 Not 100% TESTED
◇ DC OPERATING CHARACTERISTICS
(Unless otherwise specified Ta=-40～85℃, Vcc=1.7～5.5V)
Parameter
Specification
Symbol
Unit
Min. Typ. Max.
Test Condition
"H" Input Voltage1 VIH1 0.7Vcc － Vcc+1.0 V
"L" Input Voltage1 VIL1 -0.3 － 0.3Vcc V
"L" Output Voltage1 VOL1 － － 0.4 V IOL=3.0mA，2.5V≦Vcc≦5.5V（SDA）
"L" Output Voltage2 VOL2 － － 0.2 V IOL=0.7mA，1.7V≦Vcc＜2.5V（SDA）
Input Leakage Current ILI -1 － 1 μA VIN=0V～Vcc
Output Leakage Current ILO -1 － 1 μA VOUT=0V～Vcc（SDA）
Operating Current
Vcc=5.5V,fSCL=400ｋHz，tWR=5ms
ICC1 － － 2.0 mA
Byte Write,Page Write
Vcc=5.5V,fSCL=400ｋHz
ICC2 － － 0.5 mA
Random Read,Current Read,Sequential Read
Standby Current
Vcc=5.5V,SDA,SCL=Vcc
ISB － － 2.0 μA
A0,A1,A2=GND,WP=GND
○This product is not designed for protection against
○radioactive rays.
◇ AC OPERATING CHARACTERISTICS
(Unless otherwise specified Ta=-40～85℃, Vcc=1.7～5.5V)
Parameter
Symbol
Specification
Unit
Min. Typ. Max.
Clock Frequency
Data Clock High Period
Data Clock Low Period
SDA and SCL Rise Time
*1
SDA and SCL Fall Time
*1
Start Condition Hold Time
Start Condition Setup Time
Input Data Hold Time
Input Data Setup Time
Output Data Delay Time
Output Data Hold Time
Stop Condition Setup Time
Bus Free Time
Write Cycle Time
Noise Spike Width (SDA and SCL)
WP Hold Time
WP Setup Time
WP High Period
fSCL
－ － 400 kHz
tHIGH
0.6 － － μs
tLOW
1.2 － － μs
tR
－ － 0.3 μs
tF
－ － 0.3 μs
tHD:STA 0.6 － － μs
tSU:STA 0.6 － － μs
tHD:DAT 0 － － ns
tSU:DAT 100 － － ns
tPD
0.1 － 0.9 μs
tDH
0.1 － － μs
tSU:STO 0.6 － － μs
tBUF
1.2 － － μs
tWR
－ － 5 ms
tI
－ － 0.1 μs
tHD：WP 0 － － ns
tSU：WP 0.1 － － μs
tHIGH：WP 1.0 － － μs
*1 Not 100% TESTED
◇ BLOCK　DIAGRAM
A0 B3
A1 C3
64Kbit EEPROM ARRAY
13bit
ADDRESS
DECODER
SLAVE, WORD
13bit ADDRESS REGISTER
8bit
DATA
REGISTER
A2 C2
START
STOP
CONTROL LOGIC
ACK
GND C1 HIGH VOLTAGE GEN.
VCC LEVEL DETECT
Fig.-1　BLOCK　DIAGRAM
◇ PIN No., PIN NAME
A3 Vcc
A2 WP
A1 SCL
PIN No.
A1
A2
A3
B3
C3
C2
C1
B1
PIN NAME
SCL
WP
Vcc
A0
A1
A2
GND
SDA
B1 SDA
REV. A