BU9829GUL-W Datasheet, PDF (2/5 Pages) Rohm – Silicon Monolithic Integrated Circuit

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◇ MEMORY CELL CHARACTERISTICS(Ta=25℃, Vcc1=1.6～3.6V)
Parameter
Specification
Unit
Min.
Typ.
Max.
Write/Erase Cycle
*1
100,000
-
-
Cycle
Data Retention
*1
10
-
-
Year
◇ EEPROM DC OPERATING CHARACTERISTICS
(Unless otherwise specified Ta=-30～85℃, Vcc1=1.6～3.6V)
Parameter
Specification
Symbol
Unit
Min. Typ. Max.
test condition
◇ EEPROM AC OPERATING CHARACTERISTICS
(Ta=-30～85℃)
Parameter
Symbol
1.6V≦Vcc1<1.8V
Min. Typ. Max.
1.8V≦Vcc1≦3.6V
Unit
Min. Typ. Max.
"H" Input Voltage1 VIH1 0.7xVcc1 － Vcc1+0.3 V 2.5V≦Vcc1≦3.6V
SCK clock Frequency
fSCK
－
－
2.5
－
－
5 MHz
"H" Input Voltage2 VIH2 0.75xVcc1 － Vcc1+0.3 V 1.6V≦Vcc1<2.5V
SCK High Time
tSCKWH 200 －
－
80
－ － ns
"L" Input Voltage1 VIL1 -0.3 － 0.3xVcc1 V 2.5V≦Vcc1≦3.6V
SCK Low Time
tSCKWL 200 －
－
80
－ － ns
"L" Input Voltage2 VIL2 -0.3 － 0.25xVcc1 V 1.6V≦Vcc1<2.5V
CSB High Time
tCS
200
－
－
90
－ － ns
"L" Output Voltage1 VOL1 0 － 0.2 V IOL=1.0mA, 2.5V≦Vcc1≦3.6V
CSB Setup Time
tCSS 150 －
－
60
－ － ns
"L" Output Voltage2 VOL2 0 － 0.2 V IOL=1.0mA, 1.6V≦Vcc1<2.5V
CSB Hold Time
tCSH 150 －
－
60
－ － ns
"H" Output Voltage1 VOH1 Vcc1-0.2 － Vcc1 V IOH=-0.4mA, 2.5V≦Vcc1≦3.6V
SCK Setup Time
tSCKS 50
－
－
50
－ － ns
"H" Output Voltage2 VOH2 Vcc1-0.2 － Vcc1 V IOH=-100μA, 1.6V≦Vcc1<2.5V
SCK Hold Time
tSCKH 50
－
－
50
－ － ns
Input Leakage Current ILI -1 － 1 μA VIN=0V～Vcc1
SI Setup Time
tDIS
50
－
－
20
－ － ns
Output Leakage Current ILO -1 － 1 μA VOUT=0V～Vcc1 , CSB=Vcc1
SI Hold Time
tDIH
50
－
－
20
－ － ns
Vcc1=1.8V, fSCK=2MHz, tE/W=5ms
Output Data Delay Time
tPD
-
－
100
-
－ 80 ns
ICC1 - - 1.5 mA
Operating current
Byte Write，Page Write, Write Status Register Output Hold Time
tOH
0
－
-
0
－
- ns
Write
Vcc1=2.5V , fSCK=5MHz , tE/W=5ms
Output Disable Time
*1 tOZ
－
－
200
-
－ 80 ns
ICC2 - － 2.0 mA
Byte Write，Page Write, Write Status Register SCK Rise Time
*1 tRC
－
－
1
-
－
1 μs
Operating Current
Read
Vcc1=1.8V , fSCK=2MHz, SO=OPEN
ICC3 － － 0.2 mA
Read，Read Status Register
Vcc1=2.5V , fSCK=5MHz, SO=OPEN
ICC4 － － 0.6 mA
Read，Read Status Register
SCK Fall Time
Output Rise Time
Output Fall Time
Write Cycle Time
*1 tFC
－
－
1
-
－
1 μs
*1 tRO
－
－
50
-
－ 50 ns
*1 tFO
－
－
50
-
－ 50 ns
tE/W
－
－
5
－
－
5 ms
Standby Current
ISB
- － 1.0 μA Vcc1=3.6V, CSB=SCK=SI=Vcc1/GND,SO=OPEN
◇ LDO REGULATOR DC OPERATING CHARACTERISTICS
(Unless otherwise specified Ta=-30～85℃, Vcc2=2.9～3.6V)
Parameter
Specification
Symbol
Unit
Min. Typ. Max.
Test condition
Wait Time From Vcc1 on To
EEPROM Command
tON
15
－
－
15
－ － ms
*1　Not 100% TESTED
◇ LDO REGULATOR AC OPERATING CHARACTERISTICS
(Ta=-30～85℃)
Parameter
Symbol
2.9V≦Vcc≦3.6V
Unit
Min. Typ. Max.
Test condition
Output Voltage1-1 VOUT1-1 2.9 3.0 3.2 V 3.2V≦Vcc2≦3.6V, IOUT=0,2mA, VSET=1,0=[1:1] Vcc1 Rise Time
tVcc1
-
－
Output Voltage1-2 VOUT1-2 2.9 3.0 3.1 V 3.2V≦Vcc2≦3.6V, IOUT=2,10mA, VSET=1,0=[1:1] LDOEN Wait Time
tLDOEN 15
－
Output Voltage2-1 VOUT2-1 2.8 2.9 3.1 V 3.1V≦Vcc2≦3.6V, IOUT=0,2mA, VSET=1,0=[1:0]
Output Voltage2-2 VOUT2-2 2.8 2.9 3.0 V 3.1V≦Vcc2≦3.6V, IOUT=2,10mA, VSET=1,0=[1:0]
Output Voltage3-1 VOUT3-1 2.7 2.8 3.0 V 3.0V≦Vcc2≦3.6V, IOUT=0,2mA, VSET=1,0=[0:1]
Output Voltage3-2 VOUT3-2 2.7 2.8 2.9 V 3.0V≦Vcc2≦3.6V, IOUT=2,10mA, VSET=1,0=[0:1]
Output Voltage4-1 VOUT4-1 2.6 2.7 2.9
Output Voltage4-2 VOUT4-2 2.6 2.7 2.8
V 2.9V≦Vcc2≦3.6V, IOUT=0,2mA, VSET=1,0=[0:0]
V 2.9V≦Vcc2≦3.6V, IOUT=2,10mA, VSET=1,0=[0:0]
◇ BLOCK　DIAGRAM
Operating Current
Icc
- - 200 μA Vcc2=3.6V, IOUT=0A
5 msec Vcc1x0%→Vcc1x95%point
- msec Vcc1x0%point→LDOEN=High
Standby Current
ISB - - 1.0 μA Vcc2=3.6V, IOUT=0A, LDOEN=GND
"H"Input Voltage
VIH 1.4 - Vcc2+0.3 V 2.9V≦Vcc2≦3.6V
"L"Input Voltage
VIL -0.3Vcc2 - 0.6 V 2.9V≦Vcc2≦3.6V
○This product is not designed for protection against radioactive rays.
INSTRUCTION
CSB
DECODE
VOLTAGE
DETECTION
CONTROL CLOCK
SCK
WRITE
HIGH VOLTAGE
◇ PIN No. / PIN NAME
PIN No. PIN NAME
A1
Vcc1
A2
CSB
A3
SCK
B1
Vcc2
B2
SI
B3
SO
C1
VOUT
C2
GND
C3
LDOEN
SI
SO
VOUT
INSTRUCTION
REGISTER
INHIBITION GENERATOR
ADDRESS
ADDRESS
11bit
11bit
REGISTER
DECODER
DATA
R/W
8bit
8bit
REGIST
AMP
16,384 bit
EEPROM
AMP ⁺
B.R
-
RESISTOR
LDOEN
2bit
VOUT SETTING REGISTER
Fig.1　BLOCK　DIAGRAM
REV. A