BU76310AGU Datasheet, PDF (2/5 Pages) Rohm – Silicon Monolithic integrated circuit

2/4
◇Electrical characteristics
（Unless specified, Ta=25℃、AVDD=SPVDD=DVDD= 3.3V、AVSS=SPVSS=DVSS= 0V、B.W.=22Hz～22kHz、fs=48kHz、fin=1kHz）
Parameter
Symbol
Limits
Unit
Condition
MIN.
TYP.
MAX.
< Current consumption > #MASTER=0 MCLK=24MHz
Power-down mode
IDDS
-
0.03
0.1
ｍＡ #PWAP=0
Rec mode/PLL mode
IDDR
-
10.3
19
ｍＡ #MDREC=MDPLL=1
Play mode/PLL mode
IDDP
-
8.4
16
ｍＡ #MDPB=MDSP=MDPLL=1
<ＭＲＥＧ>
output voltage
VOREG 0.75AVDD-0.2 0.75AVDD 0.75AVDD+0.2
Ｖ
2.2kΩ load
< Logic interface >
Ｌ input voltage
VIL
DVSS
－
0.3DVDD
V
Ｈ input voltage
VIH
0.7DVDD
－
DVDD
V
Ｌ Input current
IIL
－
－
10
μA
Ｈ Input current
IIH
－
－
10
μA
Ｌ output voltage
VOL
0
－
0.5
V IOL=-1mA
Ｈ output voltage
VOH
DVDD-0.5 －
DVDD
V IOL=1mA
<REC path （MICIN→ADOUT）> #ALC1=OFF, MGAIN=42dB, MLIM=-37.5dB, DVOL=-4.5dB
Distortion
THD+N
62
72
-
dB DOUT=-10dBFS@1kHz
ＳＮＲ
SNR
78
88
-
dB B.W.=JIS-A
<REC path （MICIN→ADOUT）> #ALC1=OFF, MGAIN=48dB
Input impedance
ZIN
70
100
130
kΩ
Input level
VIN
-52
-50
-48
dBV DOUT=0dBFS
L/R gain mismatch
△GV
-1.0
0
+1.0
dB DOUT=0dBFS
Distortion
THD+N
43
58
-
dB DOUT=-6dBFS@1kHz
ＳＮＲ
SNR
60
66
-
dB B.W.=JIS-A
L/R separation
SEPR
58
83
-
dB DOUT=-6dBFS@1kHz
ＡＬＣ１ output level
DOALC
-
-7.3
-
dBFS ALC1=ON
<PB path1 （DAIN→LINEOUT）> #LGAIN=+5dB
Output level
VO
-5.5
-4.0
-2.5
dBV DIN=-6dBFS
L/R gain mismatch
△GV
-1.0
0
+1.0
dB DIN=-6dBFS
Distortion
THD+N
70
80
-
dB DIN=-6dBFS@1kHz
ＳＮＲ
SNR
82
90
-
dB B.W.=JIS-A
L/R separation
SEPR
80
100
-
dB DIN=-6dBFS@1kHz
<PB path2 （DAIN→EVROUT→SPIN→SPOUT BTL output）> #ALC2=OFF, EVR=-6dB, RL=8Ω
Output level
VO
1.0
3.0
5.0
dBV DIN=0dBFS
Distortion
THD+N
50
60
-
dB DIN=0dBFS@1kHz
ＳＮＲ
SNR
76
83
-
dB B.W.=JIS-A
ＡＬＣ２ output level
VOALC
1.0
3.0
5.0
dBV ALC2=ON, EVR=8dB
<PB path3 （BEEPIN→SPOUT BTL output）> #BVOL=13.5dB, RL=8Ω
Output level
GV
11.5
13.5
15.5
dB
Input impedance
ZIN
25
41
60
dB
（note） Input level of REC is relative to AVDD.
（note） Output level of PB is relative to AVDD.
（note） Input impedance oｆ BEEPIN is changed to 20kΩ～163kΩ by BVOL.
（note） Output level 3.0dBV of SPPOS/SPNEG is about 250mW at RL=8Ω.
◇Serial interface
Control commands are entered on the SEN, SCLK, and SDATA pins, using 3 line 16 bit serial input (MSB first).
The input cycle is started on the CSB falling edge, and each bit of data is read in on the SCLK rising edge.
The data is loaded to register on the CSB rising edge.
CSB
SCLK
SDATA
“x” 1 0 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 “x”
Register Address
Control Data
: A5 - A0
: D7 - D0
◇Register map
REV. A