BU2508FV_09 Datasheet, PDF (2/9 Pages) Rohm – High-precision 10bit 4ch-E6ch Type D/A Converters

BU2508FV,BU2507FV
Technical Note
●Electrical Characteristics（Unless otherwise specified, VCC＝5V, VrefH＝5V, VrefL＝0V, Ta＝25℃）
Parameter
Symbol
MIN.
Limits
TYP. MAX.
Unit
Conditions
<Digital unit>
Power source current
ICC
- 0.85 2.8
mA At CLK = 10MHz, IAO = 0uA
Input leak current
IILK -5
-
5
μA VIN=0 to VCC
Input voltage L
VIL
-
- 0.8
V
-
Input voltage H
VIH 2.0 -
-
V
-
Output voltage L
VOL 0
- 0.4
V
IOL=2.5mA
Output voltage H
VOH 4.6 -
5
V
IOH=-2.5mA
<Analog unit>
Consumption current
IrefH
-
-
4.5 7.5
2.0 3.4
mA
mA^(*1)
Data condition : at maximum current
D/A converter upper standard voltage
setting range
D/A converter lower standard voltage
setting range
VrefH 3.0 -
5
VrefL 0
- 1.5
V
Outputs does not necessarily take a
value in standard voltage setting range.
Value that output may take is in the buffer
V
amplifier output voltage range (VO).
Buffer amplifier output voltage range
VO
0.1
0.2
- 4.9
- 4.75
V
IO=±100μA
IO=±1.0mA
Buffer amplifier output drive range
IO
-2
-
2
mA
Upper saturation voltage =0.35V
Lower saturation voltage =0.23V
Differential non-linearity error DNL -1.0 -
Precision
Integral non-linearity error
Zero point error
INL -3.5
SZERO -25
-
-
Full scale error
SFULL -25 -
1.0
3.5
25
25
LSB ^{VrefH =4.796V}
VrefL=0.7V
VCC=5.5V (4mV/LSB)
mV _{No load (IO = +0mA)}
Buffer amplifier output impedance
RO
-
5 15
Ω
-
Input voltage 0V
Pull-up I/O internal resistance value
Rup 12.5 25 37.5 kΩ (Resistance value changes according
to voltage to be impressed.)
*1: Value in the case where CH1 ~ CH4 are set to maximum current
●Timing Characteristics (Unless otherwise specified, VCC＝5V, VrefH＝5V, VrefL＝0V, Ta＝25℃）
Parameter
Symbol
MIN.
Limits
TYP. MAX.
Unit
Conditions
Judgment level is 80% / 20% of VCC.
Reset L pulse width
tRTL
50
-
-
-
Clock L pulse width
tCKL
50
-
-
-
Clock H pulse width
tCKH
50
-
-
-
Clock rise time
tcr
-
-
50
-
Clock fall time
Data setup time
tcf
-
tDCH
20
-
-
50
-
nS
-
-
Data hold time
tCHD
40
-
-
-
Load setup time
tCHL
50
-
-
-
Load hold time
tLDC
50
-
-
-
Load H pulse width
tLDH
50
-
-
-
DA output settling time
tLDD
-
7
20
μS
CL≦1000pF, VO:0.5V⇔4.5V .
Until output becomes the final value 1/2LSB
RESET
tRTL
CLK
DI
LD
Output
tcr
tCKL
tCKH
tcf
tDCH tCHD
tCHL
tLDH
tLDC
tLDD
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2/8
2009.06 - Rev.A