BU24025MWV_11 Datasheet, PDF (2/5 Pages) Rohm – Silicon monolithic integrated circuit

2/4
◇3-wire serial interface
Control commands are framed by 16-bit serial input (MSB first) and input through the CSB, SCLK, and SDATA pins.
4 higher-order bits specify addresses, while the remaining 12 bits specify data.
Data of every bit is input through the SDATA pin, retrieved on the rising edges of SCLK.
Data becomes valid in the CSB Low area. The loading timing is different in the resistor. (as shown in “Note4,5”)
CSB
SCLK
SDATA ^{x D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0}
x
＜Register map＞
Address
Address[3:0]
15
14
13
12
11
10
0
0
0
0
ModeA[1:0]
0
0
0
0
0
0
0
1
0
1
1
1
0
0
1
0
EnA RtA
0
0
1
1
0
0
0
1
0
0
0
0
0
1
0
1
0
0
0
1
1
0
0
0
0
1
1
1
0
0
1
0
0
0
ModeB[1:0]
0
0
0
0
0
1
1
0
0
1
1
0
1
0
1
1
1
1
1
0
1
0
EnB RtB
1
0
1
1
0
0
1
1
0
0
0
0
0
0
1
1
0
1
0
0
0
1
0
0
0
1
1
1
1
0
1
0
1
1
Addresses other than those above
Data
Data[11:0]
9
8
7
6
5
4
3
2
1
0
SelA[1:0]
0
Ach different output voltage[6:0]
0
0
Ach Cycle[7:0]
1
0
Ach Cycle[15:8]
1
0 A_BEXC 0
0 A_BSL A_AEXC 0
0 A_ASL
1
0
0
0
APOS[1:0]
0
0
0 ASTOP
Ach Pulse[9:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SelB[1:0]
0
Bch different output voltage [6:0]
0
0
Bch Cycle[7:0]
1
0
Bch Cycle[15:8]
1
0 B_BEXC 0
0 B_BSL B_AEXC 0
0 B_ASL
0
0
0
0
3_chop[1:0]
0
0
4_chop[1:0]
1 3_PWM_Ct[1:0]
3ch PWM_Duty[6:0]
0 4_PWM_Ct[1:0]
4ch PWM_Duty[6:0]
1
0
0
0
BPOS[1:0]
0
0
0 BSTOP
Bch Pulse[9:0]
0
0
0
0
0
0
0
0
0
0
Chopping[1:0] CacheM 0
0
Isel P_CTRL
CLK_DIV[2:0]
0
0
0
0
0
0
0
0
PI_CTRL1 PI_CTRL2
1
0
0
0
0
0
5_Sel[1:0]
5_Chop[1:0]
0 5_PWM_Ct[1:0]
5ch PWM_Duty[6:0]
0
0 Current driver reference voltage adjustment6 (DAC6 output value) [7:0]
0
0 7ch_S 0 7_PWM_Ct[1:0] 6ch_S 0 6_PWM_Ct[1:0]
0
0 Current driver reference voltage adjustment7 (DAC7 output value) [7:0]
0
0
0
0
0
0
0
0
0 CMD_RS
Setting prohibited
(Note 1) The notations A, B, in the register map correspond to Ach, Bch respectively.
(Note 2) The Ach is defined as 1ch and 2ch driver output, the Bch as 3ch and 4ch driver output,
(Note 3) After resetting (Power ON reset, and CMD_RS), “initial setting” is saved in all registers.
(Note 4) For Mode, different output voltage, Cycle, En, and Rt registers, data that are written before the access to the Pulse register becomes valid,
and determined at the rising edge of CSB after the access to the Pulse register. (The Mode, different output voltage, Cycle, En, Rt, and
Pulse registers contain Cache registers, but any registers other than those do not contain with such registers.)
(Note 5) For POS, STOP, chop, PWM_Ct, and PWM_duty registers, data are determined at the rising edge of CSB, and for any registers other than
those, data are determined at the rising edge of 16th SCLK .
REV. B