BU2285FV_08 Datasheet, PDF (2/17 Pages) Rohm – DVD-Audio Reference Clock Generator for Audio/Video Appliance

●Absolute Maximum Ratings (Ta=25℃)
Parameter
Symbol
BU2285FV
BU2363FV
Unit
Supply voltage
VDD
-0.5 ～ ＋7.0
-0.5 ～ ＋7.0
V
Input voltage
VIN
-0.5 ～ VDD＋0.5
-0.5 ～ VDD＋0.5
V
Storage temperature range
Tstg
Power dissipation
PD
-30 ～ ＋125
630 ^*1
-30 ～ ＋125
℃
450 ^*2
mW
*1 In the case of exceeding at Ta = 25℃, 6.3mW should be reduced per 1℃
*2 In the case of exceeding at Ta = 25℃, 4.5mW should be reduced per 1℃
＊Operating is not guaranteed.
＊The radiation-resistance design is not carried out.
＊Power dissipation is measured when the IC is mounted to the printed circuit board.
●Recommended Operating Range
Parameter
Supply voltage
Input H voltage
Input L voltage
Operating temperature
Maximum output load
Symbol
VDD
VIH
VIL
Topr
CL
BU2285FV
3.0 ～ 3.6
0.8VDD ～ VDD
0.0 ～ 0.2VDD
-5 ～ ＋70
15
BU2363FV
Unit
3.0 ～ 3.6
V
0.8VDD ～ VDD
V
0.0 ～ 0.2VDD
V
-10 ～ ＋70
℃
15
pF
●Electrical characteristics
◎BU2285FV（VDD=3.3V, Ta=25℃, Crystal frequency 36.8640MHz, unless otherwise specified.）
Parameter
Symbol
Min.
Typ.
Max.
Unit Conditions
Output L voltage
VOL
－
－
0.4
V
IOL=4.0mA
Output H voltage
VOH
2.4
－
－
V
IOH=-4.0mA
Consumption current
IDD
－
30
50
mA At no load
CLK54M
CLK54M
－
54.0000
－
MHz XTAL×375 / 128 / 2
CLK27M
CLK27M
－
27.0000
－
MHz XTAL×375 / 128 / 4
CLKDAC
CLKDAC_H
－
CLKDAC_L
－
27.0000
13.5000
－
－
MHz
MHz
At CTRLB=OPEN,
XTAL×375 / 128 / 4
At CTRLB=L,
XTAL×375 / 128 / 8
CLK33M
CLK33M
－
33.8688
－
MHz XTAL×147 / 40 / 4
CLK16M
CLK16M
－
16.9344
－
MHz XTAL×147 / 40 / 8
CLKA
CLKA_H
CLKA_L
－
36.8640
－
MHz
At CTRLA=OPEN,
XTAL output
－
33.8688
－
MHz
At CTRLA=L,
XTAL×147 / 40 / 4
CLKB
CLKB_H
CLKB_L
－
18.4320
－
MHz
At CTRLA=OPEN,
XTAL / 2 output
－
16.9344
－
MHz
At CTRLA=L,
XTAL×147 / 40 / 8
Duty
Duty
45
50
55
%
Measured at a voltage of 1/2VDD
Period-Jitter 1σ
P-J 1σ
－
50
－
psec *1
Period-Jitter
P-J
MIN-MAX
MIN-MAX
－
300
－
psec *2
Rise Time
Tr
－
2.5
－
nsec
Period of transition time required for the
clock output to reach 80% from 20% of VDD
Fall Time
Output Lock-Time
Tf
Tlock
－
2.5
－
nsec
Period of transition time required for the
clock output to reach 20% from 80% of VDD
－
－
1
msec *3
Note) The output frequency is determined by the arithmetic (frequency division) expression of a frequency input to XTALIN.
If the input frequency is set to 36.8640MHz, the output frequency will be as listed above.
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