BU4001B_09 Datasheet, PDF (19/22 Pages) Rohm – High Voltage CMOS Logic ICs

BU4001B/F,BU4011B/F/FV,BU4030B/F,BU4070B/F,
BU4081B/F/FV,BU4093B/F/FV,BU4069UB/F/FV,BU4584B/F/FV
Technical Note
7) BU4069UB Series
I1 1
O1 2
I2 ³
O2 4
I3 5
O3 6
VEE 7
14 VDD
13 I6
12 O6
11 I5
10 _O5
9 I4
8 _O4
PIN No. PIN NAME
I/O
1
I1
I
2
O1
O
3
I2
I
4
O2
O
5
I3
I
6
O3
O
7
VSS
―
8
I4
O
9
O4
I
10
I5
O
11
O5
I
12
I6
O
13
O6
I
14
VDD
―
PIN FUNCYION
INPUT1
OUTPUT1
INPUT2
OUTPUT2
INPUT3
OUTPUT3
Power Supply(-)
OUTPUT4
INPUT4
OUTPUT5
INPUT5
OUTPUT6
INPUT6
Power Supply(+)
TRUTH TABLE
IN
OUT
H
L
L
H
8) BU4584B Series
I1 1
O1 2
I2 3
O2 4
I3 5
O3 6
VEE ⁷
14 VDD
13 I6
12 O6
11 I5
10 O5
9 I4
8 O4
PIN No.
PIN NAME
I/O
PIN FUNCYION
1
I1
I
INPUT1
2
O1
O
OUTPUT1
3
I2
I
INPUT2
4
O2
O
OUTPUT2
5
I3
I
INPUT3
6
O3
O
OUTPUT3
7
VSS
―
Power Supply(-)
8
I4
O
OUTPUT4
9
O4
I
INPUT4
10
I5
O
OUTPUT5
11
O5
I
INPUT5
12
I6
O
OUTPUT6
13
O6
I
INPUT6
14
VDD
―
Power Supply(+)
TRUTH TABLE
IN
OUT
H
L
L
H
●Notes for use
1. Absolute maximum ratings
An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break
down the devices, thus making impossible to identify breaking mode, such as a short circuit or an open circuit. If any over rated
values will expect to exceed the absolute maximum ratings, consider adding circuit protection devices, such as fuses.
2. Connecting the power supply connector backward
Connecting of the power supply in reverse polarity can damage IC. Take precautions when connecting the power supply
lines. An external direction diode can be added.
3. Power supply lines
Design PCB layout pattern to provide low impedance GND and supply lines. To obtain a low noise ground and supply line,
separate the ground section and supply lines of the digital and analog blocks. Furthermore, for all power supply terminals
to ICs, connect a capacitor between the power supply and the GND terminal. When applying electrolytic capacitors in the
circuit, not that capacitance characteristic values are reduced at low temperatures.
4. GND voltage
The potential of GND pin must be minimum potential in all operating conditions.
5. Thermal design
Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions.
6. Inter-pin shorts and mounting errors
Use caution when positioning the IC for mounting on printed circuit boards. The IC may be damaged if there is any
connection error or if pins are shorted together.
7. Actions in strong electromagnetic field
Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to malfunction.
8. Testing on application boards
When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress.
Always discharge capacitors after each process or step. Always turn the IC's power supply off before connecting it to or
removing it from a jig or fixture during the inspection process. Ground the IC during assembly steps as an antistatic
measure. Use similar precaution when transporting or storing the IC.
9. Ground Wiring Pattern
When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns,
placing a single ground point at the ground potential of application so that the pattern wiring resistance and voltage
variations caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change the
GND wiring pattern of any external components, either.
10. Unused input terminals
Connect all unused input terminals to VDD or VSS in order to prevent excessive current or oscillation.
Insertion of a resistor (100kΩ approx.) is also recommended
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2009.06 - Rev.A