BD9532EKN_08 Datasheet, PDF (19/21 Pages) Rohm – Switching Regulators for DDR-SDRAM Cores

Pin A
N
N ^P+
Parasitic element
Resistor
Pin A
P
P⁺ _N
P substrate
GND
Transistor (NPN)
Pin B _C B
Pin B
E
Parasitic
element
N _P+
Parasitic element
N
P
P⁺ _N
P substrate
GND
GND
B
C
E
Parasitic
element
GND
Other adjacent elements
Fig. 31 Example of IC structure
12. Ground Wiring Pattern
When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns, placing
a single ground point at the ground potential of application so that the pattern wiring resistance and voltage variations
caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change the GND
wiring pattern of any external components, either.
● Power Dissipation
[mW]
2500
(4)
2000 ₍₃₎
1500
1000
(2)
500 ⁽¹⁾
(1) IC unit time
θj-a=250℃/W
(2) Substrate (Substrate surface copper foil area: none)
θj-a=166.7℃/W
(3) Substrate (Substrate surface copper foil area: 60mm ×
60mm…1 layer)
θj-a=71.4℃/W
(4) Substrate (Substrate surface copper foil area: 60mm ×
60mm…2 layers)
θj-a=62.5℃/W
0
0 25 50 75 100 125 150
[℃]
Ambient temperature [Ta]
19/20