BU21170MUV Datasheet, PDF (17/33 Pages) Rohm – Capacitive Switch Controller IC

BU21170MUV
Timing Charts
Host interface
2-wire serial bus.
Compatible with I²C protocol.
Support slave mode only.
7-bit Slave Address = 0x4C (in the case of ADR = ‘L’), 0x4D (in the case of ADR = ‘H’).
Standard-mode (data transfer rate of 100kbit/s), Fast-mode (data transfer rate of 400kbit/s).
Supports sequential read.
SDA
SCL
1-7
89
1-7
8
9
1-7
89
S
P
START Address R/W ACK
Data
ACK
Data
NACK
/ ACK
STOP
Figure 8. 2-wire serial bus data format
SDA
tHD;STA
SCL
tLOW
START
condition
tSU;DAT
tHD;STA
tBUF
tHD;DAT
tHIGH
tSU;STA
repeated
START
condition
Figure 9. 2-wire serial bus data timing chart
tSU;STO
STOP
condition
START
condition
Parameter
SCL clock frequency
Hold time (repeated) START condition
LOW period of the SCL clock
HIGH period of the SCL clock
Data hold time
Data set-up time
Set-up time for a repeated START condition
Set-up time for STOP condition
Bus free time between STOP and START condition
Symbol
fSCL
tHD;STA
tLOW
tHIGH
tHD;DAT
tSU;DAT
tSU;STA
tSU;STO
tBUF
Standard-mode
MIN MAX
0
100
4.0
-
4.7
-
4.0
-
0.1
3.45
0.25
-
4.7
-
4.0
-
4.7
-
Fast-mode
MIN MAX
0
400
0.6
-
1.3
-
0.6
-
0.1
0.9
0.1
-
0.6
-
0.6
-
1.3
-
Unit
kHz
usec
usec
usec
usec
usec
usec
usec
usec
* It is necessary that interval time for writing to register which address is from 0xF0 to 0xFF is more than 650usec.
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TSZ02201-0L5L0F300830-1-2
14.Jul.2016 Rev.002