BR93G46-3 Datasheet, PDF (17/39 Pages) Rohm – Serial EEPROM series Standard EEPROM MicroWire BUS EEPROM (3-Wire)

BR93G46-3
Datasheet
4) Write enable (WEN) / disable (WDS) cycle
～～
CS
SK
1
2
34
5
67
8 _～～ n
ENABLE=1 1
DISABLE=0 0 _{～ ～}
DI
1 00
～～
DO
High-Z
For the meaning of n,please see tables of command mode in Page15.
n: required clocks
Figure 38. Write enable (WEN) / disable (WDS) cycle
○At power on, this IC is in write disable status by the internal RESET circuit. Before executing the write command, it is
necessary to execute the write enable command. And, once this command is executed, it is valid unitl the write disable
command is executed or the power is turned off. However, the read command is valid irrespective of write enable /
diable command. Input to SK after 6 clocks of this command is available by either “1” or “0”, but be sure to input it.
○When the write enable command is executed after power on, write enable status gets in. When the write disable
command is executed then, the IC gets in write disable status as same as at power on, and then the write command is
canceled thereafter in software manner. However, the read command is executable. In write enable status, even when
the write command is input by mistake, write is started. To prevent such a mistake, it is recommended to execute the
write disable command after completion of write.
5) Erase cycle (ERASE)
～～
～～
CS
tCS
STATUS
～～
～～
～～
～～
SK
12
4
～～
n
～～
～～
DI
111
Am
～ ～ ^{A3 A2 A1 A0}
～～
～～
～～
tSV
～～
DO
High-Z
BU_{～ ～}SY ^READY
tE/W
For the meaning of Am,n,please see tables of command mode in Page15.
Figure 39. Erase cycle
Am: MSB of address
n: required clocks
○In this command, data of the designated address is made into “1”. The data of the designated address
becomes “FFFFh or FFh”.
Actual ERASE starts at the fall of CS after the fall of A0 taken SK clock.
In ERASE, STATUS can be detected in the same manner as in WRITE command.
6) Erase all cycle (ERAL)
CS
SK
12
4
～～
tCS
～～ ⁿ
～～
STATUS
～～
～～
～～
～～
～～
n: required clocks
DI
DO
High-Z
1 00
1
0
～～
～～
tSV
～～
BUS_{～ ～} Y READY
tE/W
For the meaning of n,please see tables of command mode in Page15.
Figure 40. Erase all cycle
○In this command, data of all addresses is made into “1”. Data of all addresses becomes ”FFFFh or FFh”.
Actual ERASE starts at the fall of CS after the falll of the n-th clock from the start bit input.
In ERAL, STATUS can be detected in the same manner as in WRAL command.
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18.FEB.2013 REV.001