BD9673AEFJ Datasheet, PDF (17/23 Pages) Rohm – Flexible Step-down Switching Regulators with Built-in Power MOSFET

BD9673AEFJ
Datasheet
(5) Schottky diode
Recommend selecting a diode which is satisfied with maximum input voltage of the application, and which is larger
than maximum current rating. If Vf of Schottky diode is large, there is a possibility that Vf of internal parasitic diode
and Vf of Schottky diode reverse and might cause IC error operation when increasing a difference in temperature with
IC. Recommend using a diode with smaller Vf as possible, and location is recommended to be nearest to the pin.
BD9673EFJ use below diode is recommended.
品番
V_RM[V]
I_O[A]
V_F[V]
I_R[mA]
RB050L-40
40
3
0.55
1
RB055L-30
30
3
0.55
3
(6) About Adjustment of DC/DC Comparator Frequency Characteristics
Role of Phase compensation element C1, C2, R3 (See P.7. Example of Reference Application Circuit)
Stability and Responsiveness of Loop are controlled through VC Pin which is the output of Error Amp.
The combination of zero and pole that determines Stability and Responsiveness is adjusted by the combination of
resistor and capacitor that are connected in series to the VC Pin.
DC Gain of Voltage Return Loop can be calculated for using the following formula.
Adc = Rl × Gcs × AEA × ^VFB
Vout
Here, VFB is Feedback Voltage (1.0V).A_EA is Voltage Gain of Error amplifier (typ: 77dB),
Gcs is the Trans-conductance of Current Detect (typ: 10A/V), and Rl is the Output Load Resistance value.
There are 2 important poles in the Control Loop of this DC/DC.
The first occurs with/ through the output resistance of Phase compensation Capacitor (C1) and Error amplifier.
The other one occurs with/through the Output Capacitor and Load Resistor.
These poles appear in the frequency written below.
fp1 =
G_EA
2π×C1×A_EA
1
fp2 =
2π×COUT×Rl
Here, G_EA is the trans-conductance of Error amplifier (typ: 220 µA/V).
Here, in this Control Loop, one zero becomes important. With the zero which occurs because of Phase compensation
Capacitor C1 and Phase compensation Resistor R3, the Frequency below appears.
1
fz 1 =
2 π ^× C1 × R3
Also, if Output Capacitor is big, and that ESR (RESR) is big, in this Control Loop, there are cases when it has an
important, separate zero (ESR zero).
This ESR zero occurs due to ESR of Output Capacitor and Capacitance, and exists in the Frequency below.
fzESR =
1
2π× COUT ×RESR
(ESR zero)
In this case, the 3^rd pole determined with the 2^nd Phase compensation Capacitor (C2) and Phase Correction Resistor
(R3) is used in order to correct the ESR zero results in Loop Gain.
This pole exists in the frequency shown below.
1
fp 3 =
2 π × C2 × R3
(Pole that corrects ESR zero)
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TSZ22111・15・001
17/20
TSZ02201-0Q1Q0AJ00190-1-2
28.JAN.2014 Rev.003