BD91361MUV_14 Datasheet, PDF (16/27 Pages) Rohm – Synchronous Buck Converter with Integrated FET

BD91361MUV
Datasheet
(4) Calculating RITH, CITH for Phase Compensation
Since the Current Mode Control is designed to limit a inductor current, a pole (phase lag) appears in the low
frequency area due to a CR filter consisting of a output capacitor and a load resistance, while a zero (phase lead)
appears in the high frequency area due to the output capacitor and its ESR. Therefore, the phases are easily
compensated by adding a zero to the power amplifier output with C and R as described below to cancel a pole at
the power amplifier.
fp(Min)
fp 
1
2  R_O  C_O
A
Gain
[dB] ⁰
fp(Max)
IOUTMin
IOUTMax
fZ(ESR)
f_{Z ESR}

2

1
ESR C_O
Pole at power amplifier
0
Phase
[deg]
-90
Figure 34. Open Loop Gain Characteristics
When the output current decreases, the load resistance
Ro increases and the pole frequency decreases.
fp_{Min}

2

1
R_OMax  C_O
fp_{Max}

2
1
 R_OMin  C_O
Hz  with lighterload
Hz  with heavierload
A
Gain
[dB]
0
0
Phase
[deg]
-90
fZ(Amp)
Zero at power amplifier
Increasing capacitance of the output capacitor lowers the
pole frequency while zero frequency does not change.
(This is because when the capacitance is doubled, the capacitor
ESR is reduced to half.)
f_{Z Amp}

2
1
 R_ITH
 C_ITH
Figure 35. Error Amp Phase Compensation Characteristics
Rf
Cf
VCC
CIN
EN
PVCC
VCC
ADJ
CBST
ITH
L
RITH
VID<1> VID<0> GND,PGND SW
VOUT
CITH
VCC
VCC
R2
CO
R2
Figure 36. Typical Application
Stable feedback loop may be achieved by canceling the pole fp(Min) produced by the output capacitor and the load
resistance. This is done by using CR zero correction of the error amplifier.
f_{Z Amp }  f_{PMin}

1

1
2  R_ITH  C_ITH 2  R_OMAX  C_O
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06.Oct.2014 Rev.002