BU4066BC_11 Datasheet, PDF (15/18 Pages) Rohm – High Voltage CMOS Logic ICs

BU4066BC,BU4066BCF,BU4066BCFV,BU4051BC,BU4051BCF,BU4051BCFV,BU4052BC,
BU4052BCF,BU4052BCFV,BU4053BC,BU4053BCF,BU4053BCFV,BU4551B,BU4551BF,BU4551BFV
Technical Note
5) BU4551B Series
W1 1
X0 2
X1 3
X4
1Y
X0
W0
X1
W
X
Z
16 VDD
15 W0
14 W
13 Z
PIN FUNCTION
PIN No. PIN NAME I/O
PIN FUNCTION
1
W1
I/O Analog Switch Input / Output
2
X0
I/O Analog Switch Input / Output
3
X1
I/O Analog Switch Input / Output
4
X
I/O Analog Switch Input / Output
Y5
Y0 6
VEE 7
VSS 8
Y
Z1
Y0
Z0
VEE
Y1
CONTROL
12 Z1
11 _Z0
10 Y1
9 CONTROL
5
Y
I/O Analog Switch Input / Output
6
Y0
I/O
Control Input
7
VEE
-
Power Supply(-)
8
VSS
-
Power Supply(-)
9
CONTROL I
Control Input
10
Y1
I/O
Control Input
11
Z0
I/O Analog Switch Input / Output
VDD
12
Z1
I/O Analog Switch Input / Output
CONT
VSS
VEE
W0
W1
X0
X1
Y0
Y1
Z0
Z1
LE V E L
C ON V E R TE R
C ON TR OL
COMMON
W
COMMON
X
COMMON
Y
COMMON
Z
13
Z
14
W
15
W0
16
VDD
TRUTH TABLE
CONTROL
0
1
I/O Analog Switch Input / Output
I/O Analog Switch Input / Output
I/O Analog Switch Input / Output
-
Power Supply(+)
ON SWITCH
W0,X0,Y0,Z0
W1,X1,Y1,Z1
●Notes for use
1. Absolute maximum ratings
An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can
break down the devices, thus making impossible to identify breaking mode, such as short circuit or an open circuit. If any
over rated values will expect to exceed the absolute maximum ratings, consider adding circuit protection devices, such as
fuses.
2. Connecting the power supply connector backward
Connecting of the power supply in reverse polarity can damage IC. Take precautions when connecting the power supply
lines. An external direction diode can be added.
3. Power Supply lines
Design PCB layout pattern to provide low impedance GND and supply lines. To obtain a low noise ground and supply line,
separate the ground section and supply lines of the digital and analog blocks. Furthermore, for all power terminals to ICs,
connect a capacitor between the power supply and the GND terminal. When applying electrolytic capacitors in the circuit,
not that capacitance characteristic values are reduced at low temperatures.
4. GND voltage
The potential of GND pin must be minimum potential in all operating conditions.
5. Thermal design
Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions.
6. Inter-pin shorts and mounting errors
Use caution when positioning the IC for mounting on printed circuit boards. The IC may be damaged if there is any
connection error or if pins are shorted together.
7. Actions in strong electromagnetic field
Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to
malfunction.
8. Testing on application boards
When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress.
Always discharge capacitors after each process or step. Always turn the IC's power supply off before connecting it to or
remove it from a jig or fixture during the inspection process. Ground the IC during assembly steps as an antistatic measure.
Use similar precaution when transporting or storing the IC.
9.Ground Wiring Pattern
When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns,
placing a signal ground point at the ground potential of application so that the pattern wiring resistance and voltage
variations caused by large currents do not caused by large currents do not cause variations in the small signal ground
voltage. Be careful not to change the GND wiring pattern of any external components, either.
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2011.08 - Rev.B