BU24038GW_13 Datasheet, PDF (15/26 Pages) Rohm – u- step System Lens Driver for Digital Still Cameras

BU24038GW
Datasheet
＜Register map＞
Address[3:0]
Data[11:0]
15 14 13 12 11
10
9
8
7
6
5
4
3
2
1
0
0000
A_Mode[1:0]
A_SEL[2:0]
A_different_output_voltage[6:0]
0
0
0
0
A_Cycle[5:0]
0
0
0
0
1
0
A_Cycle[13:6]
0001
0
1
1
0 A_BEXC 0
0
A_BSL A_AEXC 0
0
A_ASL
1
1
1
0
0
0
A_POS[1:0]
0
0
A_PS A_Stop
0 0 1 0 A_EN A_RT
A_Pulse[9:0]
0 0 1 1 A_ACT A_BUSY B_ACT B_BUSY C_ACT C_BUSY L
L
L
L
L
L
0100
B_Mode[1:0]
B_SEL[2:0]
B_different_output_voltage[6:0]
0
0
0
0
B_Cycle[5:0]
0
0
0
0
1
0
B_Cycle[13:6]
0
1
1
0 B_BEXC 0
0
B_BSL B_AEXC 0
0
B_ASL
0101
1
0
0
0
0
0
3_CHOP[1:0]
0
0
4_CHOP[1:0]
1
0
1
3_State_CTL[1:0]
3_PWM_Duty[6:0]
1
1
0
4_State_CTL[1:0]
4_PWM_Duty[6:0]
1
1
1
0
0
0
B_POS[1:0]
0
0
B_PS B_Stop
0 1 1 0 B_EN B_RT
B_Pulse[9:0]
0111
A_Position[9:6]
B_Position[9:6]
C_Position[9:6]
1000
C_Mode[1:0]
C_SEL[2:0]
C_different_output_voltage[6:0]
0
0
0
0
C_Cycle[5:0]
0
0
0
0
1
0
C_Cycle[13:6]
1001
0
1
1
0 C_BEXC 0
0
C_BSL C_AEXC 0
0
C_ASL
1
1
1
0
0
0
C_POS[1:0]
0
0
C_PS C_Stop
1 0 1 0 C_EN C_RT
C_Pulse[9:0]
0
0
0
0
0
0
Edge
0
0
C_CTL B_CTL A_CTL
1011
0
0
1
0
0
0
0
67_SEL
0
EXT_CTL[2:0]
1100
0
0
Chopping[1:0] CacheM
0
0 CLK_EN
CLK_DIV[3:0]
0
0
0
0
0
0
0
0
0 PI_CTL3 PI_CTL2 PI_CTL1
0
0
1
0
0
0
0
0
0
0
7_CHOP[1:0]
0
1
0
7_State_CTL[1:0]
7_PWM_Duty[6:0]
0
1
1
0
1101
0
1
1
1
0
8_TARSP[7:0]
8_PSP[2:0]
0
8_ISP[2:0]
1
0
0
0
0
0
0
0
0
0
SPC_Limit[1:0]
1
0
1
0
0
0
0 8_SPEN 0
0
8_CHOP[1:0]
1
1
0
8_State_CTL[1:0]
8_PWM_Duty[6:0]
0
0
0
0
9_IOUT[7:0]
0
1
0
0
0
0
0
0
0
0
9_State_CTL[1:0]
1110
1
0
1
0
0
0
0
0
HYS4 HYS3 HYS2 HYS1
1
1
0
0
0
0
0
STB
0
0 STM_RS CMD_RS
Addresses other
than those above
Setting prohibited
(Note 1) The notations A, B, and C in the register map correspond to A-channel, B-channel and C-channel respectively.
(Note 2) The A-channel is defined as 1chl and 2ch driver output, the B-channel as 3ch and 4ch driver output, the C-channel as 5ch and 6ch driver output.
(Note 3) After reset, the initial condition is saved in all registers.
(Note 4) The addresses 4’b0011, and 4’b0111 have data (ACT, BUSY, Position [9:6]), which are internal register values and output from SOUT pin.
(Note 5) For Mode, different output voltage, Cycle, EN, and RT registers, data that are written before the access to the Pulse register becomes valid and
determines the rising edge of CSB after the access to Pulse register.
(The Mode, different output voltage, Cycle, EN, RT, and Pulse registers contain Cache registers. Any registers other than those do not contain Cache
registers.)
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TSZ22111・15・001
15/22
TSZ02201-0M2M0BC12090-1-2
18.Apr.2013 Rev.002