BR93H66-2C Datasheet, PDF (15/32 Pages) Rohm – Serial EEPROM Series Automotive EEPROM 125 Operation Microwire BUS EEPROM

BR93H66-2C
Datasheet
4. Write Enable (WEN) / Disable (WDS) Cycle
～～
CS
SK
DI
DO
High-Z
1
2
34
5
67
8 _{～ ～} 11
ENABLE=1 1
DISABLE=0 0 _{～ ～}
1 00
～～
Figure 33. Write Enable (WEN) / Disable (WDS) Cycle
(1) At power on, this IC is in Write Disable status by the internal RESET circuit. Before executing the WRITE command, it
is necessary to execute the Write Enable command first. And, once this command is executed, writing is valid until
the Write Disable command is executed or the power is turned off. However, the READ command is valid regardless
of whether the Write Enable / Disable command is executed. Input to SK after 6 clocks of this command is available
by either “H” or “L”, but be sure to input it.
(2) When the Write Enable command is executed after power on, Write Enable status gets in. When the Write Disable
command is executed then, the IC gets in Write Disable status as same as at power on, and then the WRITE
command is canceled thereafter in software manner. However, the READ command is still executable. In Write
Enable status, even when the WRITE command is input by mistake, writing will still continue. To prevent such a
mistake, it is recommended to execute the write disable command after the completion of each WRITE execution.
Application
1. Method to Cancel each Command
(1) READ
Start bit
1bit
Ope code
2bit
Address
8bit
Cancel is available in all areas in read mode.
●Method to cancel：cancel by CS =“L”
Data
16bit
Figure 34. READ Cancel Available Timing
(2) WRITE, WRAL
・Rise of 27^th clock
SK
26 27 28 29
DI D1 _D0
a
b
c
Enlarged figure
Start bit
1bit
Ope code
2bit
Address
8bit
a
Data
16bit
b
tE/W
C
a：From start bit to 27^th clock rise
Cancel by CS=“L”
b：27^th clock rise and after
Cancellation is not available by any means. If Vcc is turned OFF in this area,
designated address data is not guaranteed, therefore write once again.
c：28^th clock rise and after
Cancel by CS=“L”
However, when write is started in b area (CS is ended), cancellation is not
available by any means.
And when SK clock is input continuously, cancellation is not available.
Note 1) If Vcc is turned OFF in this area,
designated address data is not guaranteed.
Therefore, it is recommended to execute
WRITE once again.
Note 2) If CS is started at the same timing as that of
the SK rise, write execution/cancel becomes
unstable. Therefore, it is recommended to set CS to
“L” in SK=”L” area. As for SK rise, recommended
timing is of t_CSS/tC_SH or higher.
Figure 35. WRITE, WRAL Cancel Available Timing
www.rohm.com
© 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
15/29
TSZ02201-0R1R0G100030-1-2
19.DEC.2012 Rev.002