BU24035GW Datasheet, PDF (14/25 Pages) Rohm – u - step System Lens Driver for Digital Still Cameras

BU24035GW
Datasheet
●Serial interface
Control commands are framed by a 16-bit serial input (MSB first) and are sent through CSB, SCLK, and SDATA pins.
The 4 higher-order bits specify addresses, while the remaining 12 bits specify data. Data of every bit is sent through SDATA
pin, which is retrieved during the rising edge of SCLK. Data becomes valid when CSB is Low and is registered during the
rising edge of CSB.
CSB
SCLK
SDATA x D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 x
Address
Data
＜Register map＞
Address[3:0]
Data[11:0]
15 14 13 12
0000
0001
11
10
A_Mode[1:0]
0
0
0
0
0
1
0
1
1
1
0010
0100
0101
A_EN A_RT
B_Mode[1:0]
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0110
1011
1100
1101
1110
Addresses other
than those above
B_EN
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
B_RT
0
0
0
0
0
1
1
0
0
0
1
1
0
0
0
1
9
8
7
6
A_SEL[2:0]
0
0
1
0
0
0
0
0
1
0 A_BEXC 0
5
4
3
2
1
A_different_output_voltage[6:0]
A_Cycle[5:0]
0
A_Cycle[13:6]
0
0
A_Start_POS[3:0]
0
A_BSL A_AEXC 0
0
0
0
A_ASL
1
0
0
0
A_POS[1:0]
0
A_UPDW
_Stop
A_PS
A_Stop
A_Pulse[9:0] / A_UPDW_Cycle[9:0]
B_SEL[2:0]
B_different_output_voltage[6:0]
0
0
1
0
0
0
0
0
1
0 B_BEXC 0
0
0
0
0
1
3_State_CTL[1:0]
0
4_State_CTL[1:0]
B_Cycle[5:0]
0
0
B_Cycle[13.6]
0
0
B_Start_POS[3:0]
0
B_BSL B_AEXC 0
0
B_ASL
3_CHOP[1:0]
0
0
4_CHOP[1:0]
3_PWM_Duty[6:0]
4_PWM_Duty[6:0]
1
0
0
0
B_POS[1:0]
0
B_UPDW
_Stop
B_PS
B_Stop
0
0
1
0
Chopping[1:0]
B_Pulse[9:0] / B_UPDW_Cycle[9:0]
B_ANSEL A_ANSEL Edge
0
0
0
0
0
0
0
CacheM
0
5_Mode CLK_EN
0
B_CTL A_CTL
0
EXT_CTL[1:0]
CLK_DIV[3:0]
0
0
0
0
0
0
0
0 PI_CTL2 PI_CTL1
1
0 DET_SEL 0
SPEN[1:0]
0
0
0
0
1
0
TARSP[7:0]
1
1
0
PSP[2:0]
0
ISP[2:0]
0
0
0
0
0
0
SPC_Limit[3:0]
0
0
5_IOUT[7:0]
1
0
0
5_PWM_Duty[6:0]
0
0
0
0
5_CHOP[1:0]
0
0
5_State_CTL[1:0]
1
0
0
0
0
0
0
6_State_CTL[2:0]
0
0
6_IOUT[7:0]
1
0
0
0
Waveform_Vthh[5:0]
1
1
0
0
Waveform_Vthl[5:0]
0
0
0
0
0
STB
0
0 STM_RS CMD_RS
Setting prohibited
(Note 1) The notations A and B in the register map correspond to Ach and Bch respectively. Ach is defined as 1ch and 2ch driver, Bch as 3ch and 4ch driver.
(Note 2) After reset (Power ON reset), the initial condition is saved in all registers.
(Note 3) For Mode, different output voltage, Cycle, EN, and RT registers, data that are written before the access to the Pulse register becomes valid and
determines the rising edge of CSB after the access to the Pulse register.
(The Mode, different output voltage, Cycle, EN, RT, and Pulse registers contain Cache registers. Any registers other than those do not contain Cache
registers.)
www.rohm.com
© 2013 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
14/21
TSZ02201-0M2M0BC12080-1-2
18.Apr.2013 Rev.002