BR93H46RF-2LB Datasheet, PDF (14/28 Pages) Rohm – Serial EEPROM Series Industrial EEPROM 125℃ Operation Microwire BUS EEPROM (3-wire)

BR93H46RF-2LB
Datasheet
Timing Chart
1) Read Cycle (READ)
～～
～～
～～
CS
*1
～～
SK
0 12 345
～～
～～
25 26
～～
DI
DO
High-Z
1 1 0 A5
～ ～ ^{A1 A0}
～～
*2
～～
～～
0 D15 D14
～ ～ ^{D1 D0 D15 D14}
～～
*1 Start bit
When data “1” is input for the first time after the rise of CS, this will be recognized as the start bit. And, even if multiple “0” are input after the rise of CS, the first
“1” input will still be recognized as the start bit, and the following operation starts. This is common to all the commands that will be discussed hereafter.
*2 The succeeding address’ data output
（Auto-Increment Function）
Figure 30. Read Cycle
○When the READ command is recognized, the data (16bit) of the selected address is output to serial. And at that moment,
“0” (dummy bit) is output first, in sync with address bit A0 and with the rise of SK. Afterwhich, the main data is output in
sync with the rise of SK.
This IC has Address Auto Increment Function available only for READ command, wherein after executing READ
command on the first selected address, the data of the next address is read. And this will continue in a sequential order
of addresses with the use of a continuous SK clock input, and by keeping CS at “H” during auto-increment.
2) Write Cycle (WRITE)
CS
SK
0
1
2
3
4
5
DI
1 0 1 A5m
DO _High-Z
～～
～～
tCS
～～
～～
～ ～ ^A1
A0 D15 D14
～～
2ⁿ5
～～
～ ～ ^{D1 D0}
Figure 31. Write Cycle
～～
STATUS
～～
～～
～～
tSV
BUSY
～～
tE/W
READY
○In this command, input 16-bit data (D15 to D0) are written to a designated address (A5 to A0). The actual write starts
from the fall of CS, after D0 is sampled with SK clock (25th clock from the start bit input), to the rise of the 26th clock.
When STATUS is not detected (CS="L" fixed), WRITE time is 4ms (Max.) in conformity with tE/W. And when STATUS
is detected (CS="H"), all commands are not accepted for areas where "L" (BUSY) is output from D0. Therefore, do not
input any command.
Write is not made or canceled if CS starts to fall after the rise of the 26th clock.
Note: Take tSKH or more from the rise of the 25th clock to the fall of CS.
3) Write all cycle (WRAL)
CS
tCS
STATUS
SK
0
1
2
3
4
5
m₇
25n
DI
10001
DO _High-Z
B2 B1 B0 D15
D1 D0
tSV
BUSY
READY
tE/W
Figure 32. Write All Cycle
○In this command, input 16-bit data is written simultaneously to all addresses. Data is written in bulk at a write time of only
4ms (Max.) in conformity with tE/W.
The actual write starts from the fall of CS, after D0 is sampled with SK clock (25th clock from the start bit input), to the
rise of the 26th clock. If CS was ended after the rise of the 26th clock, command is canceled, and write is not
completed.
Note:Take tSKH or more from the rise of the 25th clock to the fall of CS.
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TSZ22111・15・001
14/25
TSZ02201-0R1R0G100250-1-2
27.Feb.2014 Rev.002