BD9130NV_12 Datasheet, PDF (14/20 Pages) Rohm – 2.7V to 5.5V, 2.0A 1ch Synchronous Buck Converter integrated FET

BD9130NV
Datasheet
5. Determination of output voltage
The output voltage VOUT is determined by the equation (6):
VOUT=(R2/R1+1)×VADJ・・・(6) VADJ: Voltage at ADJ terminal (0.8V Typ.)
With R1 and R2 adjusted, the output voltage may be determined as required.
Adjustable output voltage range : 1.0V to 2.5V
6
SW
1
ADJ
L
Co
Output
R2
R1
Use 1 kΩ to 100 kΩ resistor for R1.
If a resistor of the resistance higher than 100 kΩ is used,
check the assembled set carefully for ripple voltage etc.
Fig.34 Determination of output voltage
3.9
The lower limit of input voltage depends on the output voltage.
Basically, it is recommended to use in the condition :
VCCmin = VOUT+1.3V.
Fig.34. shows the necessary output current value at the lower
limit of input voltage. (DCR of inductor : 0.1Ω)
This data is the characteristic value, so it’ doesn’t guarantee the
operation range,
3.7
3.5
3.3
Vo=2.5V
3.1
Vo=1.8V
Vo=2.0V
2.9
2.7
0
0.5
1
1.5
2
OUT PUT CURRENT : IOUT [A]
Fig.35 minimum input voltage in each output voltage
Cautions on PC Board Layout
R2
R1
RITH
③
CITH
1
ADJ
2
VCC
3
ITH
4
GND
VCC
EN ⁸
EN
7
PVCC
6
L
SW
5
CIN
Co
PGND
②
①
VOUT
GND
Fig.36 Layout diagram
① For the sections drawn with heavy line, use thick conductor pattern as short as possible.
② Lay out the input ceramic capacitor CIN closer to the pins PVCC and PGND, and the output capacitor Co closer to the
pin PGND.
③ Lay out CITH and RITH between the pins ITH and GND as neat as possible with least necessary wiring.
※ SON008V5060 (BD9130NV) has thermal FIN on the reverse of the package.
The package thermal performance may be enhanced by bonding the FIN to GND plane which take a large area of
PCB.
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TSZ02201-0J3J0AJ00130-1-2
02.MAR.2012 Rev.001