BU9795AKS2 Datasheet, PDF (13/40 Pages) Rohm – Standard LCD Segment Drivers

BU9795Axxx Series MAX 140 segments (SEG35×COM4)
Datasheet
<BU9795AFV>
This LSI has Display Data RAM (DDRAM) of 27×4=108bit.
As SEG0, SEG1, SEG2, SEG3, SEG31, SEG32, SEG33, SEG34 are not output, these address will be dummy address.
The relationship between data input and display data, DDRAM data and address are as follows.
Command
0000000
abcd e fg h i j k l mn o pq r s t u vxy _…
Dummy data
Display Data
8 bit data will be stored in DDRAM. The address to be written is the address specified by ADSET command, and the
address is automatically incremented in every 4bit data.
Data can be continuously written in DDRAM by transmitting Data continuously.
(When RAM data is written successively after writing RAM data to 22h (SEG34), the address is returned to 00h (SEG0)
by the auto-increment function.
Dummy data
DDRAM address
Dummy data
00h 01h 02h 03h 04h 05h 06h 07h ・・・・・・・ 1Eh 1Fh 20h 21h 22h
0a e i m q u
COM0
1b f j n r v
BIT
2c g k o s x
COM1
COM2
3d h l p t y
COM3
SEG
0
SEG
1
SEG
2
SEG
3
SEG
4
SEG
5
SEG
6
SEG
7
・・・・・・・
SEG
30
SEG
31
SEG
32
SEG
33
SEG
34
As data transfer to DDRAM happens every 4bit data, it will be cancelled if it changes CSB=“L”→”H” before
4bits data transfer.
CSB
SCL
SD
Internal signal
RAM write
Command
Address set
RAM write
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Address00h
Address01h
Address02h
Write data will be
canceled, when CSB='H'
RAM write (Every 4bit data)
without
4bit data transfer.
CSB
SCL
SD
Internal signal
RAM write
Command
Address set
RAM write
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Address00h
Address21h
Address22h
Address00h
Return to address "0"
by automatically
increment.
Figure 18. BU9795AFV Data Transfer Format
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12.July.2012 Rev.002