BU6520KV Datasheet, PDF (13/19 Pages) Rohm – Video Encoders built-in Image Correction

BU6520KV,BU6521KV
Technical Note
2. The 2 line formula serial interface format
Slave address is 70h.
The sub-address is incremented automatically when accessing it (read / write) continuously 2 times or more.
SSDDA I
SSDCCLK _S
1-7
8
START Slave
condition address
R/W
9
1-7
8
9
1-7
8
ACK
Sub address ACK
Data
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9
P
ACK
STOP
condition
Write sequence
S
Slave address
(70h)
W
(0)
A(S)
Sub address
A(S)
Data
A(S)
Data
A(S)
Data
A(S)/
NA(S)
P
Read sequence
S
Slave address
(70h)
W
(0)
A(S)
Sub address
A(S) S
Slave address
(70h)
R
(1)
A(S)
Data
A(M)
Data
A(M)/
NA(M)
P
S = START condition
P = STOP condition
A(S) = Acknowledge by slave
A(M) = Acknowledge by master
NA(S) = Not acknowledge by slave
NA(M) = Not acknowledge by master
3. SPI-bus format
Fig.12 2-line serial interface format
WPB H'/'L' level is set by the REG_WPB register.
SCEB H'/'L' level is set by the REG_SCEB register.
SCK
SDO
W7 W6 W5 W4 W3 W2 W1 W0
SDI
R7 R6 R5 R4 R3 R2 R1 R0
The data written in
the SWDATA register is set.
It is possible to read it
from the SRDATA register.
Fig.13 SPI-bus interface wave form
* REG_WPB, REG_SCEB, SWDATA, and SRDATA in figure are the register names, and the each function is as follows.
REG_WPB ：Set WP Terminal logic. Register value is output directly.
REG_SCEB ：Set SCEB Terminal logic. Register value is output directly.
SWDATA[7:0]：Write data to EEPROM. Transfers MSB the first.
SRDATA[7:0] ：Read data from EEPROM. Converts MSB the first.
The SCK clock frequency is as follows.
SCK frequency = CAMCKI frequency ÷ 2^{(SPIPREDIV+1)} ÷ (SPIDIV+1)
Register range : SPIPREDIV = 0 to 7, SPIDIV = 0 to 31
When CAMCKI is 27MHz, SCK becomes 3.3 kHz from 13.5 MHz.
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13/18
2010.02 - Rev.C