BH3874AKS2 Datasheet, PDF (13/25 Pages) Rohm – Sound processor IC

Audio ICs
!Circuit operations
Timing of Control Signal
SCK
(CLOCK signal)
35pin
34pin
SI
DATA signal
LATCH signal
90%
tw
tw
10%
tsu
th
tw(DATA)
90%
10%
BH3874AKS2
ts
tw(LATCH)
90%
10%
Fig.2
DATA (SI) is read at a rising edge of CLOCK.
DATA is fixed by the rising edge of LATCH.
Be sure to set SCK and SI to Low after latching.
When the CLOCK signal is High, it doesn’t accept LATCH signal.
Constant of Timing Chart (Ta=25°C)
Parameter
Symbol
Min.
Typ.
Max. Unit
"High" Input voltage
VIH
3.3
5.0
6.0
V
"Middle" Input voltage
"Low" Input voltage
Clock width
Data width
Latch width
VIM
1.8
2.0
2.4
V
VIL
−0.3
0
1.2
V
tw
2.0
−
−
µs
tw (DATA) 4.0
−
−
µs
tw (LATCH) 2.0
−
−
µs
Setup time (DATA→CLOCK)
tsu
1.0
−
−
µs
Hold time (CLOCK→CLOCK)
Setup time (DATA, CLOCK→LATCH)
th
1.0
−
−
µs
ts
1.0
−
−
µs
∗ Serial signal SI is judging DATA and LATCH in the difference of the voltage level.
∗ In the application schematic, it is changing 0-5V 3 line serial data into the 2 line serial data at the voltage with the resistance and
the diode of the external.
We request enough examination, because there is a case where the voltage which is changed by the ability for the microcomputer to
drive and the external parts.