BH3866AS Datasheet, PDF (13/25 Pages) Rohm – Dual-line serial control sound processor IC

Video ICs
BH3866AS
Slave address
MSB
LSB
10000010
Parameter
Bass boost gain, Lch
I²C
BUS
Symbol
SW NO.
Selected address / data
Measurement
1 2 3 4 5 6 7 8 9 10 11 0 0 0 1 0 2 0 3 0 4 0 5 0 6 ^point
VBMAXL 1 1 1 2 1 1 2 1 1 1 — F F 0 0 0 0 7 F 2 0 0 0 0 C B
Bass boost gain, Cch
VBMAXC 1 1 1 1 2 1 1 2 1 1 — 0 0 0 0 F F 7 F 2 0 0 0 0 C B
Bass cut gain, Rch
VBMINR 1 1 2 1 1 2 1 1 1 1 — 0 0 F F 0 0 0 0 2 0 0 0 0 C B
Bass cut gain, Lch
VBMINL 1 1 1 2 1 1 2 1 1 1 — F F 0 0 0 0 0 0 2 0 0 0 0 C B
Bass cut gain, Cch
VBMINC 1 1 1 1 2 1 1 2 1 1 — 0 0 0 0 F F 0 0 2 0 0 0 0 C B
Treble boost gain, Rch
VTMAXR 1 1 2 1 1 2 1 1 1 1 — 0 0 F F 0 0 2 0 7 F 0 0 0 C B
Treble boost gain, Lch
VTMAXL 1 1 1 2 1 1 2 1 1 1 — F F 0 0 0 0 2 0 7 F 0 0 0 C B
Treble boost gain, Cch
VTMAXC 1 1 1 1 2 1 1 2 1 1 — 0 0 0 0 F F 2 0 7 F 0 0 0 C B
Treble cut gain, Rch
VTMINR 1 1 2 1 1 2 1 1 1 1 — 0 0 F F 0 0 2 0 0 0 0 0 0 C B
Treble cut gain, Lch
VTMINL 1 1 1 2 1 1 2 1 1 1 — F F 0 0 0 0 2 0 0 0 0 0 0 C B
Treble cut gain, Cch
VTMINC 1 1 1 1 2 1 1 2 1 1 — 0 0 0 0 F F 2 0 0 0 0 0 0 C B
AGC input / output level 1, Rch VAGC1R 1 1 2 2 1 2 1 1 1 1 — F F F F 0 0 2 0 2 0 0 0 0 1 B
AGC input / output level 1, Lch VAGC1L 1 1 2 2 1 1 2 1 1 1 — F F F F 0 0 2 0 2 0 0 0 0 1 B
AGC input / output level 2, Rch VAGC2R 1 1 2 2 1 2 1 1 1 1 — F F F F 0 0 2 0 2 0 0 0 0 1 B
AGC input / output level 2, Lch VAGC2L 1 1 2 2 1 1 2 1 1 1 — F F F F 0 0 2 0 2 0 0 0 0 1 B
AGC input / output level 3, Rch VAGC3R 1 1 2 2 1 2 1 1 1 1 — F F F F 0 0 2 0 2 0 0 0 0 1 B
AGC input / output level 3, Lch VAGC3L 1 1 2 2 1 1 2 1 1 1 — F F F F 0 0 2 0 2 0 0 0 0 1 B
AGC input / output level 4, Rch VAGC4R 1 1 2 2 1 2 1 1 1 1 — F F F F 0 0 2 0 2 0 0 0 0 1 ^B
AGC input / output level 4, Lch VAGC4L 1 1 2 2 1 1 2 1 1 1 — F F F F 0 0 2 0 2 0 0 0 0 1 B
Total harmonic distortion at AGC ON, Rch THDAGCR 1 1 2 2 1 2 1 1 1 1 — F F F F 0 0 2 0 2 0 0 0 0 1 C
Total harmonic distortion at AGC ON, Lch THDAGCL 1 1 2 2 1 1 2 1 1 1 — F F F F 0 0 2 0 2 0 0 0 0 1 C
Max. surround gain, Rch
VSUMAXR 1 1 2 1 1 2 1 1 1 1 — 0 0 F F 0 0 2 0 2 0 C F 0 0 B
Max. surround gain, Lch
VSUMAXL 1 1 1 2 1 1 2 1 1 1 — F F 0 0 0 0 2 0 2 0 C F 0 0 B
Min. surround gain, Rch
VSUMINR 1 1 2 1 1 2 1 1 1 1 — 0 0 F F 0 0 2 0 2 0 C 0 0 0 B
Min. surround gain, Lch
VSUMINL 1 1 1 2 1 1 2 1 1 1 — F F 0 0 0 0 2 0 2 0 C 0 0 0 B
Surround gain at Loop ON, Rch VLPSUR 1 1 2 1 1 2 1 1 1 1 — 0 0 F F 0 0 2 0 2 0 D 6 0 0 B
Surround gain at Loop ON, Lch VLPSUL 1 1 1 2 1 1 2 1 1 1 — F F 0 0 0 0 2 0 2 0 D 6 0 0 B
Bass Add ON gain, Rch
Bass Add ON gain, Lch
Pseudo-stereo gain, Rch
Pseudo-stereo gain, Lch
DAC pin operating voltage 1
DAC pin operating voltage 2
Suction current at I²C BUS ACK
SCL and SDA pin input high level
SCL and SDA pin input low level
VBAONR
VBAONL
VMONR
VMONL
VDAC1
VDAC2
IACK
VIHI
VILO
1 1 2 1 1 2 1 1 1 1—0 0 F F 0 0 2 0 2 0 0 0 1 0 B
1 1 1 2 1 1 2 1 1 1—F F 0 0 0 0 2 0 2 0 0 0 1 0 B
1 1 2 2 1 2 1 1 1 1—F F F F 0 0 2 0 2 0 A F 0 0 B
1 1 2 2 1 1 2 1 1 1—F F F F 0 0 2 0 2 0 A F 0 0 B
1111111112100000020200020 H
1111111112200000020200000 H
1 1 1 1 1 1 1 1 1 1—
G
1 1 1 1 1 1 1 1 1 1—
EF
1 1 1 1 1 1 1 1 1 1—
EF
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