BD9122GUL_12 Datasheet, PDF (13/19 Pages) Rohm – 2.5V to 5.5V, 0.3A 1ch Synchronous Buck Converter integrated FET

0J3J0AJ00110
Datasheet
4. Determination of RITH, CITH that works as a phase compensator
As the Current Mode Control is designed to limit a inductor current, a pole (phase lag) appears in the low frequency area
due to a CR filter consisting of a output capacitor and a load resistance, while a zero (phase lead) appears in the high
frequency area due to the output capacitor and its ESR. So, the phases are easily compensated by adding a zero to the
power amplifier output with C and R as described below to cancel a pole at the power amplifier.
A
Gain
[dB] ⁰
0
Phase
[deg]
-90
fp(Min.)
fp(Max.)
IOUTMin.
IOUTMax.
fz(ESR)
fp=
1
2π×RO×CO
fz(ESR)=
1
2π×ESR×CO
Pole at power amplifier
When the output current decreases, the load resistance Ro
increases and the pole frequency lowers.
Fig.31 Open loop gain characteristics
fp(Min.)=
1
2π×ROMax.×CO
[Hz]←with lighter load
fp(Max.)=
1
2π×ROMin.×CO
[Hz] ←with heavier load
A
Gain
[dB]
0
0
Phase
[deg]
-90
fz(Amp.)
Zero at power amplifier
Increasing capacitance of the output capacitor lowers the pole
frequency while the zero frequency does not change. (This is
because when the capacitance is doubled, the capacitor ESR
reduces to half.)
fz(Amp.)=
1
2π×RITH×CITH
Fig.32 Error amp phase compensation characteristics
VCC
Cin
L
EN
VCC,PVCC
SW
VOUT
VOUT
VOUT
ESR
RO
ITH
GND,PGND
CO
RITH
CITH
Fig.33 Typical application
Stable feedback loop may be achieved by canceling the pole fp (Min.) produced by the output capacitor and the load
resistance with CR zero correction by the error amplifier.
fz(Amp.)= fp(Min.)
1
2π×RITH×CITH
=
1
2π×ROMax.×CO
5. Determination of output voltage
The output voltage VOUT is determined by the equation (7):
VOUT=(R2/R1+1)×VADJ・・・(7) VADJ: Voltage at ADJ terminal (0.8V Typ.)
With R1 and R2 adjusted, the output voltage may be determined as required.
SW
L
Co
Output
R2
Adjustable output voltage range : 1.0V to 2.0V
Use 1 kΩ to 100 kΩ resistor for R1. If a resistor of the resistance higher than
ADJ
R1
Fig.34 Determination
of output voltage
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