BU90RT102 Datasheet, PDF (12/19 Pages) Rohm – 70bit LVDS Distributor

BU90RT102
●AC Timing Diagram
t_TOP0
t_TOP1
t_TOP2
t_TOP3
t_TOP4
t_{TOP 5}
t_{TOP 6}
Technical Note
Tyx +/-
D<6> D<5> D<4> D<3> D<2> D<1> D<0>
t _TCP
t_TCH
t_TCL
TCLKx +
TCLKx -
x=1,2
y= A,B,C,D,E
Ty1 +/- output timing is the one between TCLK 1 +/- and Ty1 +/- .
Ty2 +/- output timing is the one between TCLK 2 +/- and Ty2 +/- .
80 ％
Vdifft
20 ％
80 ％
20 ％
Note
1) Vdifft =(Ty+)-(Ty-)
=A,B,C,CLK,D,E
y=1,2
t_LVT
t _LVT
Fig.8 AC Timing Diagram (2)
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12/18
2010.10 - Rev.A