BD26503GUL Datasheet, PDF (12/44 Pages) Rohm – 7x17(Max ) Dot Matrix LED Display Driver

BD26503GUL
Technical Note
(5) Writing protocol
A register address is transferred by the next 1 byte that transferred the slave address and the write-in command. The
3rd byte writes data in the internal register written in by the 2nd byte, and after 4th byte or, the increment of register
address is carried out automatically. However, when a register address turns into the last address (77h), it is set to 00h
by the next transmission. After the transmission end, the increment of the address is carried out.
*1
*1
S X X X X X X X 0 A A7 A6 A5 A4 A3 A2 A1 A0 A D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 A P
slave address
register address
DATA
DATA
R/W =0(write)
register address
increment
register address
increment
from master to slave
from slave to master
A=acknowledge(SDA LOW)
A=not acknowledge(SDA HIGH)
S=START condition
P=STOP condition
*1: Write Timing
(6) Timing diagram
SDA
t LOW
t SU;DAT
t HD;STA
t BUF
SCL
t HD;STA
S
t HD;DAT
t HIGH
t SU;STA
Sr
t SU;STO
P
S
Fig.9 Timing diagram (I2C format)
(7) Electrical Characteristics(Unless otherwise specified, Ta=25 ^oC, VBAT=3.6V, VINSW=3.6V, VIO=1.8V)
Parameter
【I²C BUS format】
Symbol
Standard-mode
Min. Typ. Max.
Fast-mode
Min.
Typ. Max.
Unit
SCL clock frequency
fSCL
0
-
100
0
-
400
kHz
LOW period of the SCL clock
tLOW
4.7
-
-
1.3
-
-
μs
HIGH period of the SCL clock
tHIGH
4.0
-
-
0.6
-
-
μs
Hold time (repeated) START condition
After this period, the first clock is generated
tHD;STA
4.0
-
-
0.6
-
-
μs
Set-up time for a repeated START
condition
Data hold time
tSU;STA
4.7
tHD;DAT
0
-
-
0.6
-
3.45
0
-
-
μs
-
0.9
μs
Data set-up time
Set-up time for STOP condition
tSU;DAT 250
-
-
100
-
tSU;STO
4.0
-
-
0.6
-
-
ns
-
μs
Bus free time between a STOP
and START condition
tBUF
4.7
-
-
1.3
-
-
μs
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2013.02 - Rev.A