BD9C301FJ-LB Datasheet, PDF (11/22 Pages) Rohm – 4.5V to 18V Input, 3.0A Integrated MOSFET Single Synchronous Buck DC/DC Converter

BD9C301FJ-LB
PCB Layout Design
In the step-down DC/DC converter, a large pulse current flows into two loops. The first loop is the one into which the current
flows when the top FET is turned ON. The flow starts from the input capacitor C_IN, runs through the FET, inductor L and
output capacitor C_OUT and back to GND of C_IN via GND of C_OUT. The second loop is the one into which the current flows
when the bottom FET is turned on. The flow starts from the bottom FET, runs through the inductor L and output capacitor
C_OUT and back to GND of the bottom FET via GND of C_OUT. Route these two loops as thick and as short as possible to
allow noise to be reduced for improved efficiency. It is recommended to connect the input and output capacitors directly to
the GND plane. The PCB layout has a great influence on the DC/DC converter in terms of all of the heat generation, noise
and efficiency characteristics.
V_IN
C_IN
MOS FET
L
V_OUT
C_OUT
GND
Figure 21. Current Loop of Buck Converter
Accordingly, design the PCB layout considering the following points.
 Connect an input capacitor as close as possible to the IC VIN pin on the same plane as the IC.
 If there is any unused area on the PCB, provide a copper foil plane for the GND node to assist heat dissipation from
the IC and the surrounding components.
 Switching nodes such as SW are susceptible to noise due to AC coupling with other nodes. Route the coil pattern as
thick and as short as possible.
 Provide lines connected to FB and COMP far from the SW nodes.
 Place the output capacitor away from the input capacitor in order to avoid the effect of harmonic noise from the input.
Vout
SW
L
IC
GND
VIN
Top layer
Mid layer1
Mid layer2
Bottom layer
Figure 22. Example of evaluation board layout
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TSZ22111・15・001
11/19
TSZ02201-0J3J0AJ00540-1-2
21.Feb.2014 Rev.002