BM94801KUT Datasheet, PDF (100/379 Pages) Rohm – Initial Program ROM

BM94801KUT
Datasheet
RXCSR in Host Mode – continued
Bits
Name
Direction Reset
5
ReqPkt
R/W
0x0
4
FlushFIFO
R/W
0x0
3
DataError/
NAK Timeout
R/W
0x0
2
Error
R/W
0x0
1
FIFOFull
0
RxPktRdy
R
0x0
R/W
0x0
Description
CPU sets this bit to “1” to request an IN transaction. It is
cleared when RxPktRdy is set.
The CPU sets this bit to “1” to flush the next packet to be
read from the endpoint Rx FIFO.
The FIFO pointer is reset and the RxPktRdy bit (below) is
cleared. Note: FlushFIFO should only be used when
RxPktRdy is set. At other times, it may cause data to be
corrupted. Also note that, if the FIFO is double-buffered,
FlushFIFO may need to be set twice to completely clear
the FIFO.
When operating in ISO mode, this bit is set to “1” when
RxPktRdy is set if the data packet has a CRC or bit-stuff
error and cleared when RxPktRdy is cleared.
In Bulk mode, this bit will be set to “1” when the Rx
endpoint is halted following the receipt of NAK responses
for longer than the time set as the NAK Limit by the
RxInterval register. The CPU should clear this bit to allow
the endpoint to continue.
The USB sets this bit to “1” when 3 attempts have been
made to receive a packet and no data packet has been
received. The CPU should clear this bit. An interrupt is
generated when the bit is set. Note: This bit is only valid
when the Tx endpoint is operating in Bulk or Interrupt
mode. In ISO mode, it always returns zero.
This bit is set to “1” when no more packets can be loaded
into the Rx FIFO.
This bit is set to “1” when a data packet has been
received. The CPU should clear this bit when the packet
has been unloaded from the Rx FIFO. An interrupt is
generated when the bit is set.
RxCount
RxCount is a 16-bit read-only register, which holds the number of received data bytes in the packet currently in line to be
read from the Rx FIFO. If the packet was transmitted as multiple bulk packets, the number given will be for the combined
packet.
Note: The value returned changes as the FIFO is unloaded and is only valid while RxPktRdy (RxCSR.D0) is set.
Offset: 0x18
Width: 16 bits
Bits
Name
Direction Reset
Description
15:13
-
N/A
12:0
Endpoint Rx
Count
R
0x0 -
0x0 Endpoint Rx Count
TxType(Host Mode Only)
Offset: 0x1A
Width: 6 bits
Bits
Name
Direction
5:4
Protocol
R/W
Target
3:0
Endpoint
R/W
Number
Reset
2'h0
4'h0
Description
The CPU sets these bits to select the required protocol for
the Tx endpoint:
00: Illegal
01: Isochronous
10: Bulk
11: Interrupt
The CPU should set this value to the endpoint number
contained in the Tx endpoint descriptor returned to the
MUSBHDRC during device enumeration.
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18.Apr.2014 Rev.003