BU9833GUL-W_10 Datasheet, PDF (10/19 Pages) Rohm – WL-CSP EEPROM family I2C BUS

BU9833GUL-W
Technical Note
●Command
○Read cycle
Data of EEPROM is read. In read cycle, there are random read cycle and current read cycle.
Random read cycle is a command to read data by designating address, and is used generally.
Current read cycle is a command to read data of internal address register without designating address, and is used when
to verify just after write cycle. In both the read cycles, sequential read cycle is available, and the next address data next
address data can be read in succession.
SDA
LINE
S
W
S
T
R
T
R
S
A
I
A
E
T
R
SLAVE
T
T ^ADDRESS E
WORD
ADDRESS(n)
R
SLAVE
A
T ^ADDRESS D
DATA(n)
O
P
1 0 1 0 A2 0 0
WA
7
RA
/C
WK
WA
0
1 0 1 0 A2 0 0
D7
A
RA
C
/C
K
WK
D0
A
C
K
Fig.39 Random Read cycle
SDA
LINE
S
T
A
R
T
SLAV E
ADDRESS
R
E
A
D
1 0 1 0 A2 0 0
D7
RA
/C
WK
S
T
DATA
O
P
D0
A
C
K
Fig.40 Current read cycle
SDA
LINE
S
T
A
R
T
SLAVE
ADDRESS
R
E
A
D
1 0 1 0 A2 0 0
D7
DATA(n)
D0
S
T
DATA(n+x)
O
P
D7
D0
RA
A
A
A
/C
C
C
C
WK
K
K
K
Fig.41 Sequential read cycle
It is necessary to input “H”
to the last ACK.
It is necessary to input “H”
to the last ACK.
・In random read cycle, data of designated word address can be read.
・When the command just before current read cycle is random read cycle, current read cycle (each including sequential
read cycle), data of incremented last read address (n-th) address, i.e., data of the (n+1)-th address is output.
・When ACK signal “LOW” after D0 is detected, and stop condition is not sent from the master (μ-COM) side, the next
address data can be read in succession.
・Read cycle is ended by stop condition where “H” is input to ACK signal after D0 and SDA signal is started at SCL
signal “H”.
・When “H” is not input to ACK signal after D0, sequential read gets in, and the next data is output.
Therefore, read command cycle cannot be ended. When to end read command cycle, be sure input stop condition to
input “H” to ACK signal after D0, and to start SDA at SCL signal “H”.
・Sequential read is ended by stop condition where “H” is input to ACK signal after arbitrary D0 and SDA is started at SCL
signal “H”.
Note)
1 0 1 0 A2 0 0
Fig.42 Difference of slave address of each type
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10/18
2010.10 - Rev.A