BU6520KV_10 Datasheet, PDF (10/19 Pages) Rohm – Video Encoders built-in Image Correction

BU6520KV,BU6521KV
3. 2-line Serial Interface Timing
Technical Note
SDA
SDC
tLOW
t SU ;D A T
t H D ;ST
tBUF
t H D ;STA
tHD;DAT
t H IGH
tSU;STA
Fig.7 2-line Serial Interface Timing
t SU ;STO
Symbol
Description
MIN TYP MAX Unit
f_SCL
t_HD;STA
f_LOW
SDC Clock Frequency
Hold Time (repetition) ”START” conditions.
The first clock pulse is generated after this period.
The ”L” period of SDC clock
0
-
400 kHz
0.6
-
-
µs
1.3
-
-
µs
t_HIGH
The ”H” period of SDC clock
0.6
-
-
µs
t_SU;STA
Setup Time of repetitive ”START” conditions
0.6
-
-
µs
t_HD;DAT
Data Hold Time
0
µs
t_SU;DAT
Data Setup Time
100
-
-
ns
t_SU;STO
Setup Time of the ”STOP” conditions
0.6
-
t_BUF
Bus free Time between ”STOP” conditions and the ”START”
conditions
1.3
-
-
µs
-
µs
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10/18
2010.02 - Rev.C