BD48E23G-MTR Datasheet, PDF (10/17 Pages) Rohm – Standard CMOS Voltage Detector IC

BD48Exxx-M series BD49Exxx-M series
Datasheet
●Application Information
Explanation of Operation
For both the open drain type (Fig.12) and the CMOS output type (Fig.13), the detection and release voltages are used as
threshold voltages. When the voltage applied to the VDD pins reaches the applicable threshold voltage, the VOUT terminal
voltage switches from either “High” to “Low” or from “Low” to “High”. Please refer to the Timing Waveform and Electrical
Characteristics for information on hysteresis. Because the BD48Exxx-M series uses an open drain output type, it is
necessary to connect a pull-up resistor to VDD or another power supply if needed [The output “High” voltage (VOUT) in this
case becomes VDD or the voltage of the other power supply].
V DD
R1
Vref
R2
RL
V OUT
Q1
R3
GND
Fig.12 (BD48Exxx-M series Internal Block Diagram)
R1
Vref
V DD
Q2
V OUT
R2
Q1
R3
GND
Fig.13 (BD49Exxx-M series Internal Block Diagram)
Reference Data
Examples of Leading (tPLH) and Falling (tPHL) Output
Part Number
tPLH (µs)
tPHL (µs)
BD48E45G-M
39.5
87.8
BD49E45G-M
32.4
52.4
*This data is for reference only.
VDD=4.3V 5.1V
VDD=5.1V 4.3V
The figures will vary with the application, so please confirm actual operating conditions before use.
Timing Waveform
Example: the following shows the relationship between the input voltages VDD and the output voltage VOUT when the
input power supply voltage VDD is made to sweep up and sweep down (the circuits are those in Fig.12 and 13).
VDD
VDET+ΔVDET
VDET
VOPL
0V
VOUT
VOH
tPHL
VOL
⑤
tPLH
tPHL
tPLH
①②③ ④
Fig.14 Timing Waveform
1 _{When the power supply is turned on, the output is unstable}
from after over the operating limit voltage (VOPL) until tPHL.
Therefore it is possible that the reset signal is not valid when the
rise time of VDD is faster than tPHL.
2 _{When VDD is greater than VOPL, but less than the reset release}
voltage (VDET + ∆VDET), the output voltages will switch to Low.
3 _{If VDD exceeds the reset release voltage (VDET + ∆VDET), then,}
VOUT switches from L to H.
4 _{If VDD drops below the detection voltage (VDET) when the power}
supply is powered down or when there is a power supply
fluctuation, VOUT switches to L (with a delay of tPHL).
5 _{The potential difference between the detection voltage and the}
release voltage is known as the hysteresis width (∆VDET).
The system is designed such that the output does not toggle with
power supply fluctuations within this hysteresis width, preventing
the
malfunctions due to noise.
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TSZ22111・15・001
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TSZ02201-0R7R0G300070-1-2
22.May.2013.Rev.003