BD37068FV-M Datasheet, PDF (1/34 Pages) Rohm – AEC-Q100 Qualified

Datasheet
Analog Sound Processors series
Sound Processor for car audio
built-in High-Voltage function and
2^nd order post filter
BD37068FV-M
Structure
It is built-in input selector of 6 stereo source and output
to ADC after adjusting signal level. And built-in 2^nd order
post filter to reduce out of band noise and 6ch Volume
circuit. It is possible to out until 5.2Vrms at maximum
output. (High Voltage function) Moreover, it is simple to
design set by built-in TDMA noise reduction systems.
Feature
Built-in differential input selector that can select
single-ended / differential input
Reduce the shock noise when switching gain due to
built-in advanced switch circuit
Decrease the out of band noise of DAC by built-in 2nd
order post filter.
Built-in buffered ground isolation amplifier to realize
high CMRR characteristics
No need to countermeasure using external
components built-in TDMA noise reduction circuit
It is possible to output 5.2Vrms by High-Voltage
function
Package is SSOP-B40. Putting same direction
input-terminals and output-terminals make PCB
layout easier and PCB area smaller.
It is possible to control by 3.3V for I²C-BUS
controller
AEC-Q100 Qualified.
Applications
It is the optimal for the car audio. Besides, it is
possible to use for the audio equipment of mini
Compo, micro Compo, TV.
Key Specifications
Total harmonic distortion：
Maximum input voltage：
Common mode rejection ratio：
Maximum output voltage：
Output noise voltage：
Residual output noise voltage：
Ripple rejection:
Operating temperature range:
0.003%
2.2Vrms(Typ)
55dB(Min)
5.2Vrms(Typ)
23µVrms(Typ)
10.5µVrms(Typ)
-70dB (Typ)
-40℃ to +85℃
※The above electrical characteristic is condition
High-Voltage mode.
Package
SSOP-B40
W(Typ) x D(Typ) x H(Max.)
13.60mm x 7.80mm x 2.00mm
Typical Application Circuit
VCCL
10μ
OUTC OUTS OUTR1 OUTR2 OUTF1 OUTF2 INF2 INF1 INR2 INR1 INS INC IG1 IG2
VREF GND SDA
10μ 10μ 10μ 10μ 10μ 10μ 2.2μ 2.2μ 2.2μ 2.2μ 2.2μ 2.2μ 10μ 10μ
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
10μ
25
24
23
SCL
22
SSOP-B40
VCCH
10μ
21
Level
Shift
Level
Shift
Level
Shift
Level
Shift
Level
Shift
Level
Shift
100k 100k 100k
100k 100k 100k
Reg
I2C-BUS LOGIC
Sub SEL
2nd order LPF
Rear SEL
Front
SEL
Main Gain adjust
Sub
Gain adjust
■fader : +23dB～-79dB、-∞/1dBstep
■InputGain : +23dB～-15dB/1dBstep
* No POP Noise
■2nd order LPF: fc=70kHz
■Main/Sub Gain Adjust 0dB/6dB
■Anti-TDMA noise circuit
■High-Voltage Output
* Input Gain
100k
Input selector (1 single - end and 5 stereo ISO)
GND
GND
GND
ISO amp ISO amp ISO amp
GND
ISO amp
GND
ISO amp
GND
ISO amp
GND
ISO amp
GND
ISO amp
100k 250k 250k 250k 250k
250k 250k
250k
250k 250k 250k
250k 250k
GND
ISO amp
250k 250k
GND
ISO amp
250k 250k
100k
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
2.2μ 2.2μ 2.2μ 2.2μ 2.2μ 10μ 2.2μ 2.2μ 10μ 2.2μ 2.2μ 10μ 2.2μ 2.2μ 10μ 10μ 2.2μ 2.2μ 10μ
A1
A2
BP1
BP2 CP1 CN CP2 DP1 DN
DP2 EP1 EN EP2 FP1 FN1 FN2 FP2 MIN BN HIVOLB
Figure 1. Application Circuit Diagram
○Product structure：Silicon monolithic integrated circuit ○This product is not designed protection against radioactive rays.
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TSZ02201-0C2C0E100130-1-2
13.MAR.2014 Rev.001