RS5C372B-E2-F Datasheet, PDF (31/57 Pages) RICOH electronics devices division – I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC

RS5C372A/B
1.2-3 Data transmission format in I²C bus
I²C bus generates no CE signals. In place of it each device has a 7bit slave address allocated. The first 1byte is
allocated to this 7bit of slave address and to the command (R/ W) for which data transmission direction is designated
by the data transmission thereafter. 7bit address is sequentially transmitted from the MSB and 2 and after bytes are
read, when 8bit is “H” and write when “L”.
The slave address of the RS5C372A/B are specified at (0110010).
At the end of data transmission/receiving stop condition is generated to complete transmission. However, if start
condition is generated without generating stop condition, repeated start condition is met and transmission/receiving
data may be continued by setting the slave address again. Use this procedures when the transmission direction
needs to be changed during one transmission.
Data is written into
the slave from the master
S
When data is read from
the slave immediately
S
after 7bit addressing
from the master
Slave address 0 A
Data
(0110010)
R/W=0 (Write)
Slave address 1 A
Data
(0110010)
R/W=1 (Read)
When the transmission
direction is to be changed S
during transmission.
Slave address 0 A
Data
(0110010)
R/W=0 (Write)
A
Data
A
Data
A
Data
AP
A
Data
AP
Inform read has been completed by
not generating an acknowledge signal,
to the slave side.
A Sr Slave address 1
(0110010) R/W=1 (Read)
AP
Master to slave
S Start condition
Inform read has been completed by
not generating an acknowledge signal, to the slave side.
Slave to master
P Stop condition
A A A Acknowledge signal
Sr Repeated start condition
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