RS5C372B Datasheet, PDF (27/39 Pages) RICOH electronics devices division – I2C-bus Serial Interface Real Time Clock (8pin SSOP)

RS5C372B
3. Oscillation Halt Sensing
Oscillation halt can be sensed through monitoring the XSTP bit with preceding setting of the XSTP bit
to 0 by writing data to the control register 2. Upon oscillator halt sensing, the XSTP bit is switched
from 0 to 1. This function can be applied to judge clock data validity. When the XSTP bit is 1, /XSL,
F6 to F0, CT2, CT1, CT0, AALE, BALE, /CLEN and TEST bit are reset to 0.
1) The XSTP bit is set to 1 upon power-on from 0V.Note that any instantaneous power disconnection
may cause operation failure.
2) Once oscillation halt has been sensed, the XSTP bit is held at 1 even if oscillation is restarted.
Considerations in Use of XSTP Bit
Ensure error-free oscillation halt sensing by preventing the following events:
1) Instantaneous disconnection of VDD
2) Condensation on the crystal oscillator
3) Generation of noise on the PCB in the crystal oscillator
4) Application of voltage exceeding prescribed maximum ratings to the individual pins of the IC.
4. /INTR output pins
The following two output wave forms can be output from the /INTR pin.
1) Alarm Interrupt
When a registered time for alarm (such as day-of-the-week, hour or minute) coincide with calendar
counter (such as day-of-the-week, hour or minute) interrupt to the CPU are requested with the output
pin being on (“L”). Alarm interrupt consists of Alarm_A and Alarm_B, both have equivalent functions.
2) Periodic Interrupt
Outputs an output wave form selected by setting the periodic interrupt frequency select bit. Wave
forms include pulse mode and level mode.
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