R2023K Datasheet, PDF (24/50 Pages) RICOH electronics devices division – 2-wire Serial Interface Real Time Clock IC

R2023K/T
(3) Data Transmission Format in I²C-Bus
I²C-Bus has no chip enable signal line. In place of it, each device has a 7bit Slave Address allocated. The first
1byte is allocated to this 7bit address and to the command (R/W) for which data transmission direction is
designated by the data transmission thereafter. 7bit address is sequentially transmitted from the MSB and 2 and
after bytes are read, when 8bit is “H” and when write “L”.
The Slave Address of the R2023K/T is specified at (0110010).
At the end of data transmission / receiving, Stop Condition is generated to complete transmission. However, if start
condition is generated without generating Stop Condition, Repeated Start Condition is met and transmission /
receiving data may be continue by setting the Slave Address again. Use this procedure when the transmission
direction needs to be change during one transmission.
Data is written to the slave
from the master
When data is read from the
slave immediately after 7bit
addressing from the master
When the transmission
direction is to be changed
during transmission.
S Slave Address 0 A
Data
A
Data
AP
(0110010)
R/W =0(W rite)
S Slave Address 1 A
Data
A
Data
/A P
(0110010)
R/W =1(Read)
Inform read has been completed by not generate
an acknowledge signal to the slave side.
S Slave Address 0 A
Data
(0110010)
R/W =0(W rite)
A Sr Salve Address 1
(0110010) R/W=1(Read)
A
Data
A
Data
/A P
Master to slave
S Start Condition
Inform read has been completed by not generate
an acknowledge signal to the slave side.
Slave to master
A A /A ^{Acknowledge Signal}
P ^{Stop Condition}
Sr ^{Repeated Start Condition}
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