RS5C321A Datasheet, PDF (21/33 Pages) RICOH electronics devices division – ULTRA-COMPACT SERIAL REAL-TIME CLOCK ICs WITH 32.768kHz

5. CE Pin
SCLK/SCLK *
SIO
CE
Shift clock pulses
Address Data
Write Data
Read Data
Read control bit
Control bit
*^{) RS5C321A: SCLK}
RS5C321B: SCLK
RS5C321A/B
1) Switching the CE pin to the high level enables the SCLK/SCLK and SIO pins, allowing data to be serially read
from and written to the SIO pin in synchronization with shift clock pulses input from the SCLK/SCLK pin.
2) Switching the CE pin to the low level or opening disables the SCLK/SCLK and SIO pins, causing high imped-
ance and resetting the internal interfacing circuits such as the shift register. While data of the address register
and bank bit which have been written just before should be preserved.
3) The CE pin should be held at the low level or open state when no access is made to the RS5C321A/B.
The CE pin incorporates a pull-down resistor.
4) During system power-down (being back-up battery powered), the low-level input of the CE pin should be brought
as close as possible to the VSS level to minimize the loss of charge in the battery.
5) The CE pin should be held at the low level in order to be enable oscillator halt sensing. Holding the CE pin at
the high level, therefore, disables oscillator halt sensing, retaining the value of the XSTP (oscillator halt sensing)
bit which exists immediately before the CE pin is switched to the high level.
Considerations
When the power turns on from 0V, the CE pin should be set low or open once.
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